AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 36

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 5-1.
36
Virtual
address
[31:29]
111
110
101
100
0xx
AVR32
Segment
name
P4
P3
P2
P1
P0 / U0
The virtual address map
The P3 space is also by default segment translated to the physical address range 0x00000000
to 0x1FFFFFFF. By enabling and setting up the MMU, the P3 space becomes page translated.
Page translation will override segment translation.
The P4 space is intended for memory mapping special system resources like the memory arrays
in caches. This segment is non-cacheable, non-translated.
The U0 segment is accessible in the unprivileged user mode. This segment is cacheable and
translated, depending upon the configuration of the cache and the memory management unit. If
accesses to other memory addresses than the ones within U0 is made in application mode, an
access error exception is issued.
The virtual address map is summarized in
The segment translation can be disabled by clearing the S bit in the MMUCR. This will place all
the virtual memory space into a single 4 GB mapped memory space. Doing this will give all
access permission control to the AP bits in the TLB entry matching the virtual address, and allow
all virtual addresses to be translated. Segment translation is enabled by default.
The AVR32 architecture has two translations of addresses.
Both these translations are performed by the MMU and they can be applied independent of each
other. This means that you can enable:
The segment translation is by default turned on and the page translation is by default turned off
after reset. The segment translation is summarized in
Virtual
Address Range
0xFFFF_FFFF to
0xE000_0000
0xDFFF_FFFF to
0xC000_0000
0xBFFF_FFFF to
0xA000_0000
0x9FFF_FFFF to
0x8000_0000
0x7FFF_FFFF to
0x0000_0000
1. Segment translation (enabled by the MMUCR[S] bit)
2. Page translation (enabled by the MMUCR[E] bit)
1. No translation. Virtual and physical addresses are the same.
2. Segment translation only. The virtual and physical addresses are the same for
3. Page translation only. All addresses are mapped as described by the TLB entries.
4. Both segment and page translations. P1 and P2 are mapped to the physical address
addresses residing in the P0, P4 and U0 segments. P1, P2 and P3 are mapped to the
physical address range 0x00000000 to 0x1FFFFFFF.
range 0x00000000 to 0x1FFFFFFF. U0, P0 and P3 are mapped as described by the
TLB entries. The virtual and physical addresses are the same for addresses residing in
the P4 segment.
Segment
size
512 MB
512 MB
512 MB
512 MB
2 Gb
Accessible
from
Privileged
Privileged
Privileged
Privileged
Unprivileged
Privileged
Table 5-1 on page
Yes
Yes
Default
segment
translated
No
Yes
No
Figure 5-2 on page
36.
Characteristics
System space
Unmapped, Uncacheable
Mapped,
Cacheable
Unmapped, Uncacheable
Unmapped, Cacheable
Mapped, Cacheable
37.
32000D–04/2011