AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 84

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.3.2.9
8.3.2.10
84
AVR32
INT2 Exception
INT1 Exception
The INT2 exception is generated when the INT2 input line to the core is asserted. The INT2
exception can be masked by the SR[GM] bit, and the SR[I2M] bit. Hardware automatically sets
the SR[I2M] bit when accepting an INT2 exception, inhibiting new INT2 requests when process-
ing an INT2 request.
The INT2 Exception handler address is calculated by adding EVBA to an interrupt vector offset
specified by an interrupt controller outside the core. The interrupt controller is responsible for
providing the correct offset.
Since the INT2 exception is unrelated to the instruction stream, the instructions in the pipeline
are allowed to complete. After finishing the INT2 exception routine, execution should continue at
the instruction following the last completed instruction in the instruction stream.
The INT1 exception is generated when the INT1 input line to the core is asserted. The INT1
exception can be masked by the SR[GM] bit, and the SR[I1M] bit. Hardware automatically sets
the SR[I1M] bit when accepting an INT1 exception, inhibiting new INT1 requests when process-
ing an INT1 request.
The INT1 Exception handler address is calculated by adding EVBA to an interrupt vector offset
specified by an interrupt controller outside the core. The interrupt controller is responsible for
providing the correct offset.
Since the INT1 exception is unrelated to the instruction stream, the instructions in the pipeline
are allowed to complete. After finishing the INT1 exception routine, execution should continue at
the instruction following the last completed instruction in the instruction stream.
RSR_INT2 = SR;
RAR_INT2 = Address of first noncompleted instruction;
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’100;
SR[I2M] = 1;
SR[I1M] = 1;
SR[I0M] = 1;
PC = EVBA + INTERRUPT_VECTOR_OFFSET;
RSR_INT1 = SR;
RAR_INT1 = Address of first noncompleted instruction;
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’011;
SR[I1M] = 1;
SR[I0M] = 1;
PC = EVBA + INTERRUPT_VECTOR_OFFSET;
32000D–04/2011