AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 8

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2.5
2.6
2.6.1
8
Entry and Exit Mechanism
Register File
AVR32
Register file in AVR32A
anisms are in place to make sure the nonsecure software can not read or modify instruction or
data belonging to the secure software. The secure state is described in chapter 4.
Table 2-4 on page 8
Table 2-4.
Each of AVR32’s normal operation modes described in
page 7
the Link Register (LR) are mapped into the register file, making the effective register count for
each context 13 general purpose registers. The mapping of SP, PC and LR allows ordinary
instructions, like additions or subtractions, to use these registers. This results in efficient
addressing of memory.
Register R12 is designed to hold return values from function calls, and the conditional return
with move and test instruction use this register as an implicit return value operand. The load mul-
tiple and pop multiple instructions have the same functionality, which enables them to be used
as return instructions.
The AVR32 core’s orthogonal instruction set allows all registers in the register file to be used as
pointers.
The AVR32A is targeted for cost-sensitive applications. Therefore, no hardware-shadowing of
registers is provided, see
states are placed on the system stack, not in dedicated registers as done in AVR32B. A shad-
owed stack pointer is still provided for the privileged modes, facilitating a dedicated system
stack.
When an exception occurs in an AVR32A-compliant implementation, the status register and
return address are pushed by hardware onto the system stack. When an INT0, INT1, INT2 or
INT3 occurs, the status register, return address, R8-R12 and LR are pushed on the system
stack. The corresponding registers are popped from stack by the rete instruction. The scall and
rets instructions also use the system stack to store the return address and status register.
Non-maskable Interrupt
Exception Mode
Interrupt3
Interrupt2
Interrupt1
Interrupt0
Supervisor Mode
Application Mode
Subprogram
Secure state
has a dedicated context. Note that the Stack Pointer (SP), Program Counter (PC) and
Entry and exit from states, modes and functions
illustrates how the different states and modes are entered and exited.
Figure 2-2 on page
Entry method
Signal on NMI line
Internal error signal generated
Signal on INT3 line
Signal on INT2 line
Signal on INT1 line
Signal on INT0 line
scall instruction
Returned to from any of the above modes
Function call
sscall
9. All data that must be saved between execution
Section 2.4.1 “Normal RISC State” on
Exit method
rets
rete
rete
rete
rete
rete
rete
Can not be exited from
ret{cond}, ldm, popm,
mov PC, LR
retss
32000D–04/2011