AD9644 Analog Devices, AD9644 Datasheet - Page 23

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AD9644

Manufacturer Part Number
AD9644
Description
14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9644

Resolution (bits)
14bit
# Chan
2
Sample Rate
155MSPS
Analog Input Type
Diff-Bip
Ain Range
1.75 V p-p
Adc Architecture
Pipelined
Data Sheet
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 57. The
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518/AD9520/AD9522
performance.
CLOCK
CLOCK
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor (see Figure 58).
CLOCK
Input Clock Divider
The AD9644 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. For
divide ratios other than 1 the duty cycle stabilizer is automatically
enabled.
The AD9644 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. The AD9644 requires a tight
tolerance on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9644 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the perfor-
mance of the AD9644. Noise and distortion performance are
nearly flat for a wide range of duty cycles with the DCS enabled.
1
INPUT
INPUT
INPUT
50Ω RESISTOR IS OPTIONAL.
Figure 58. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
Figure 57. Differential LVDS Sample Clock (Up to 640 MHz)
50Ω
0.1µF
1
0.1µF
0.1µF
50kΩ
V
CC
1kΩ
1kΩ
AD95xx
LVDS DRIVER
AD95xx
CMOS DRIVER
clock drivers offer excellent jitter
OPTIONAL
100Ω
0.1µF
100Ω
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9510/
ADC
ADC
Rev. C | Page 23 of 44
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit. The
loop has a time constant associated with it that must be considered
in applications in which the clock rate can change dynamically.
A wait time of 1.5 μs to 5 μs is required after a dynamic clock
frequency increase or decrease before the DCS loop is relocked to
the input signal. During the time period that the loop is not locked,
the DCS loop is bypassed, and internal device timing is dependent
on the duty cycle of the input clock signal. In such applications, it
may be appropriate to disable the duty cycle stabilizer. In all other
applications, enabling the DCS circuit is recommended to
maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. For inputs near full scale, the degradation in
SNR from the low frequency SNR (SNR
frequency (f
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 59. The measured curve in
Figure 59 was taken using an ADC clock source with approxi-
mately 65 fs of jitter, which combines with the 125 fs of jitter
inherent in the AD9644 to produce the result shown.
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9644.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the
Note (visit www.analog.com) for more information about jitter
performance as it relates to ADCs.
SNR
75
70
65
60
55
50
1
HF
= −10 log[(2π × f
AN-501
INPUT
Figure 59. SNR vs. Input Frequency and Jitter
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
) due to jitter (t
Application Note and the
INPUT FREQUENCY (MHz)
10
INPUT
JRMS
× t
) can be calculated by
JRMS
)
100
LF
2
) at a given input
+ 10
AN-756
(
SNR
LF
AD9644
Application
/
10
)
1000
]

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