AD9644 Analog Devices, AD9644 Datasheet - Page 8

• Manufacturer Part Number: AD9644
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9644

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 155MSPS
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined

AD9644
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Conversion Rate
DATA OUTPUT PARAMETERS
Wake Up Time (Power-Down)
TERMINATION CHARACTERISTICS
OUT-OF-RANGE RECOVERY TIME
1
2
Conversion rate is the clock rate after the divider.
Wake-up time is defined as the time required to return to normal operation from power-down mode.
Random Jitter at 1.6 Gbps
Random Jitter at 3.2 Gbps
Output Rise/Fall Time
Differential Termination Resistance
Input Clock Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Pipeline Delay (Latency)
Data Rate per Channel (NRZ)
Deterministic Jitter
Data Output Period or UI (Unit Interval)
Data Output Duty Cycle
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8
Data Valid Time
PLL Lock Time (t
Wake Up Time (Standby)
Mode
1
A
)
LOCK
)
CH
)
2
J
)
CLK
)
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Rev. C | Page 8 of 44
Min
40
12.5
3.75
5.95
0.8
23
AD9644-80
Typ
6.25
6.25
0.78
0.125
1/(20 × f
50
0.78
4
5
2.5
1.6
40
9.5
5.2
50
100
2
CLK
)
Max
640
80
8.75
6.55
24
Min
40
6.45
1.935
3.065
0.8
23
AD9644-155
Typ
3.225
3.225
0.78
0.125
1/(20 × f
50
0.74
4
5
2.5
3.1
40
5.2
50
100
2
CLK
)
Data Sheet
Max
640
155
4.515
3.385
24
Unit
MHz
MSPS
ns
ns
ns
ns
ns
ps rms
Seconds
%
UI
µs
µs
ms
CLK
cycles
Gbps
ps
ps rms
ps rms
ps
Ω
CLK
cycles