AD9644 Analog Devices, AD9644 Datasheet - Page 27

• Manufacturer Part Number: AD9644
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9644

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 155MSPS
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined

Data Sheet
Table 11. AD9644 JESD204A Frame Alignment Monitoring and Correction Replacement Characters
Scrambling
Off
Off
Off
On
On
On
Frame and Lane Alignment Monitoring and Correction
Frame alignment monitoring and correction is part of the
JESD204A specification. The 14-bit word requires two octets to
transmit all the data. The two octets (MSB and LSB), where
F = 2, make up a frame. During normal operating conditions
frame alignment is monitored via alignment characters, which
are inserted under certain conditions at the end of a frame.
Table 11 summarizes the conditions for character insertion
along with the expected characters under the various operation
modes. If lane synchronization is enabled, the replacement
character value depends on whether the octet is at the end of a
frame or at the end of a multiframe.
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replacement characters.
Digital Outputs and Timing
The AD9644 has differential digital outputs that power up
by default. The driver current is derived on chip and sets the
output current at each output equal to a nominal 4 mA. Each
output presents a 100 Ω dynamic internal termination to reduce
unwanted reflections.
A 100 Ω differential termination resistor should be placed at
each receiver input to result in a nominal 400 mV peak-to-peak
swing at the receiver (see Figure 66). Alternatively, single-ended
50 Ω termina-tion can be used. When single-ended termination
is used, the termination voltage should be DRVDD/2; otherwise,
ac coupling capacitors can be used to terminate to any single-
ended voltage.
The AD9644 digital outputs can interface with custom ASICs
and FPGA receivers, providing superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a single differential 100 Ω termination
resistor placed as close to the receiver logic as possible. The
Lane Synchronization
On
On
Off
On
On
Off
Character to be Replaced
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame equals D28.7 (0xFC)
Last octet in frame equals D28.3 (0x7C)
Last octet in frame equals D28.7 (0x7C)
Rev. C | Page 27 of 44
common mode of the digital output automatically biases itself
to half the supply of the receiver (that is, the common-mode
voltage is 0.9 V for a receiver supply of 1.8 V) if dc-coupled
connecting is used (see Figure 67). For receiver logic that is not
within the bounds of the DRVDD supply, an ac-coupled
connection should be used. Simply place a 0.1 μF capacitor on
each output pin and derive a 100 Ω differential termination
close to the receiver side.
If there is no far-end receiver termination or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches and that the differential output traces be
close together and at equal lengths.
OUTPUT SWING = 400mV p-p
OUTPUT SWING = 400mV p-p
DOUT+x
DOUT–x
DRVDD
Figure 67. DC-Coupled Digital Output Termination Example
Figure 66. AC-Coupled Digital Output Termination Example
DOUT+x
DOUT–x
DRVDD
0.1µF
0.1µF
Last Octet in
Multiframe
No
Yes
Not applicable
No
Yes
Not applicable
DIFFERENTIAL
DIFFERENTIAL
TRACE PAIR
TRACE PAIR
100Ω
100Ω
100Ω
100Ω
Replacement Character
K28.7 (0xFC)
K28.3 (0x7C)
K28.7 (0xFC)
K28.7 (0xFC)
K28.3 (0x7C)
K28.7 (0xFC)
V
OR
RXCM
RECEIVER
V
V
CM
CM
RECEIVER
= Rx V
= DRVDD/2
AD9644
CM