AD9644 Analog Devices, AD9644 Datasheet - Page 36

• Manufacturer Part Number: AD9644
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9644

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 155MSPS
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined

AD9644
Addr
(Hex)
0x24
0x25
0x3A
JESD204A Configuration Registers
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
Register
Name
BIST signature
LSB (local)
BIST signature
MSB (local)
Sync control
(global)
JESD204A
quick
configure
(global)
JESD204A
lane
assignment
(global)
JESD204A
Link Control
Register 1
(local)
JESD204A
Link Control
Register 2
(local)
JESD204A
Link Control
Register 3
(local)
JESD204A
Link Control
Register 4
(local)
JESD204A
device
identification
number (DID)
(local)
Bit 7
(MSB)
Open
Open
Open
Open
Disable
CHKSUM
00 = individual mode
Local DSYNC mode
10 = DSYNC active
01 = global mode
11 = DSYNC pin
disabled
mode
Bit 6
Open
Open
Open
Serial
tail bit
enable
Open
Bit 5
Open
Open
Open
Serial test
sample enable
DSYNC pin
input inverted
00 = 16-bit data injected at
01 = 10-bit data injected at
Link test generation input
output of 8b/10b encoder
sample input to the link
JESD204A serial device identification (DID) number
10 = reserved
11 = reserved
Initial lane assignment sequence repeat count
selection
Bit 4
Open
Open
Open
Serial
lane
synchro
nization
enable
CMOS
DSYNC
input
0 =
LVDS
1 =
CMOS
Rev. C | Page 36 of 44
BIST signature[15:8]
BIST signature[7:0]
Bit 3
Open
Open
Open
Open
0010 = two lanes per link. Link A: Lane 0, Lane 1 sent on
0011 = two lanes per link. Link A: Lane 0, Lane 1 sent on
0100 = two lanes per link. Link B: Lane 0, Lane 1 sent on
Serial lane alignment
0000 = one lane per link. Link A: Lane 0 sent on Lane A,
0001 = one lane per link. Link A: Lane 0 sent on Lane B,
0101 = two lanes per link. Link B: Lane 0, 1 sent on
11 = always on test
sequence mode
00 = disabled
10 = reserved
01 = enabled
mode
Lane A, Lane B. Link B disabled.
Lane B, Lane A. Link B disabled.
Lane A, Lane B. Link A disabled.
Lane B, Lane A. Link A disabled.
Link B: Lane 0 Sent on Lane A.
Link B: Lane 0 Sent on Lane B
JESD204A serial lane control
Bit 2
Clock
divider
next sync
only
Bypass
8b/10b
encoding
010 = two converters using one link with
011 = two converters using one link and
101 = user test pattern data continuous
0110 to 1111: reserved
001 = two converters using two links
110 = user test pattern data single
001 = alternating checker board
determined by other registers
000 = default—configuration
100 = PN sequence—short
Link test generation mode
011 = PN sequence—long
000 = normal operation
010 = 1/0 word toggle
with one lane per link
100 to 111: reserved
111 = ramp output
two lanes per link
a single lane
Bit 1
Clock
divider
sync
enable
Frame
alignment
character
insertion
disable
Invert
transmit
bits
Bit 0
(LSB)
Master sync
buffer
enable
Serial
transmit link
powered
down
Mirror serial
output bits
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Data Sheet
Default/
Comments
Read only
Read only
Changes
settings of
Address
0x5F to
Address
0x60 and
Address
0x6E to
Address
0x72
(self
clearing)