ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 150
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.6.3 D Event detection
In sensorless mode, the D Window Filter becomes
active after each C event. It blanks out the D event
during the time window defined by the DWF[3:0]
bits in the MDFR register (see
value is 200µs.
This Window Filter becomes active after both
hardware and software C events.
The D Event Filter becomes active after the D Win-
dow Filter. It counts the number of consecutive D
events up to a limit defined by the DEF[3:0] bits in
the MDFR register. The reset value is 1. The D bit
is set when the counter limit is reached.
Sampling is done at a selectable frequency
(f
The D event filter is active only for a hardware D
event (D
to 1.
Figure 79.
150/309
1
SCF
), see
Reset counter
H
). For a simulated (D
D Window and Event Filter Flowchart
Table
No
No
No
Increment counter
Blanking Window
Counter=Limit?
82.
Set the D bit
Sampling
Yes
End of
Event
C
D
?
?
Yes
No
Table
S
) event, it is forced
WINDOW
26). The reset
FILTER
FILTER
EVENT
Yes
Limit=1?
Yes
Note: Times are indicated for 4 MHz f
Table 27. D Event filter Setting
DWF3 DWF2 DWF1 DWF0
DEF3 DEF2 DEF1 DEF0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C to D window fil-
ter in Sensorless
D event Limit
Mode (SR=0)
100 µs
120 µs
140 µs
160 µs
180 µs
200 µs
10 µs
15 µs
20 µs
25 µs
30 µs
35 µs
40 µs
60 µs
80 µs
5 µs
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PERIPH
SR=1
SR=1
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