ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 268
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 144. RESET pin protection when LVD is enabled.
Figure 145. RESET pin protection when LVD is disabled.
Note 1:
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
Note 5: Please refer to
268/309
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
EXTERNAL
device can be damaged when the ST7 generates an internal reset (LVD, illegal opcode or watchdog).
below the V
internally.
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
section 12.2.2 on page
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”
RESET
Required
EXTERNAL
CIRCUIT
RESET
USER
Required
IL
max. level specified in
0.01μF
“Illegal Opcode Reset” on page 244
248.
0.01μF
1MΩ
Optional
(note 3)
section 12.9.1 on page
V
V
DD
DD
R
R
for more details on illegal opcode reset conditions
ON
ON
Filter
Filter
267. Otherwise the reset will not be taken into account
1)2)3)4)
GENERATOR
1)
GENERATOR
PULSE
PULSE
WATCHDOG
ILLEGAL OPCODE
LVD RESET
WATCHDOG
ILLEGAL OPCODE
INTERNAL
RESET
INTERNAL
RESET
INJ(RESET)
ST72XXX
ST72XXX
5)
5)
in
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