ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 31
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
6.2.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f
A proper reset signal for a slow rising V
can generally be provided by an external RC net-
work connected to the RESET pin.
Figure 16. RESET Sequences
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
V
V
IT+(LVD)
IT-(LVD)
V
RUN
DD
ACTIVE PHASE
DD
RESET
LVD
is over the minimum
OSC
frequency.
DD
RUN
t
h(RSTL)in
supply
WATCHDOG UNDERFLOW
ACTIVE
PHASE
EXTERNAL
RESET
6.2.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■
■
The device RESET pin acts as an output that is
pulled low when V
V
The LVD filters spikes on V
avoid parasitic resets.
6.2.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
DD
Power-On RESET
Voltage Drop RESET
<V
IT-
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
(falling edge) as shown in
RUN
ACTIVE
PHASE
WATCHDOG
RESET
t
w(RSTL)out
w(RSTL)out
DD
ST7MC1xx/ST7MC2xx
<V
DD
IT+
RUN
.
larger than t
CPU
(rising edge) or
)
Figure
Figure
g(VDD)
16.
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