ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 160
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Depending on the frequency and the duty cycle of
the PWM signal, the delay inserted before sam-
pling could cause it sample the signal OFF time in-
stead of the ON time. In this case an interrupt can
be generated and the sample will not be taken into
acount. When a sample occurs outside the PWM
signal ON time, the SOI bit in the MCONF register
is set and an interrupt request is generated if the
SOM bit is set in the MCONF register. This inter-
rupt is enabled only if a delay value has been set in
the DS[3:0] bits. In this case, the sampling is done
at the PWM frequency but only during the ON time
of the PWM signal.
in detail the generation of the sampling order when
the delay is added.
Figure 84. Adding the Delay to sample during ON time for Z detection
Figure 85. Sampling Out interrupt generation
160/309
1
PWM signal
Figure 84
PWM signal
T
Sampling
PWM OFF
time
and
Figure 85
T
Sampling
PWM OFF
time
Current
sample
DS[3:0]
shows
DS[3:0]
For complete flexibility, the possibility of sampling
at f
PWM signal is also available when the SPLG bit is
set as if there is a delay value in the DS[3:0] bits.
This means that when the sampling is to be per-
formed, after the delay a sampling window at f
frequency is opened until the next OFF time of the
PWM signal. The Sampling Out interrupt will be
generated if the delay added is longer than the
duty cycle of the PWM signal. As the SPLG bit is
set and a value has been put in the DS[3:0] bits,
no minimum off time is required for the PWM sig-
nal and it is automatically set to 0µs in current
mode. A true 100% duty cycle can be also set in
the 12-bit Timer in voltage mode.
in detail the sampling at f
ing ON time.
Current
sample
SO
DS[3:0]
SCF
high frequency during the ON time of the
SO
New sample during next
OFF time. Sample not taken into
account. SO interrupt generated.
sample
New
To interrupt generator
SCF
high frequency dur-
Figure 86
shows
SCF
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