TMPM363F10FG Toshiba, TMPM363F10FG Datasheet
TMPM363F10FG
Specifications of TMPM363F10FG
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TMPM363F10FG Summary of contents
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... Bit RISC Microcontroller TX03 Series TMPM363F10FG ...
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... TOSHIBA CORPORATION All Rights Reserved ...
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... ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. ************************************************************************************************************************* TMPM363F10FG R ...
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... This register does not exist in this microcontroller. b. SFR(register) ・ Each register basically consists of a 32-bit register (some exceptions). ・ The description of each register provides bits, bit symbols, types, initial values after reset and func- tions. Register name SAMCR TMPM363F10FG Base Address = 0x0000_0000 Address(Base+) 0x0004 0x000C ...
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... Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width TDATA Function READ WRITE TMPM363F10FG MODE ...
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... TMPM363F10FG ...
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Date Revision 2011/4/13 Tentative 1 2011/6/23 1 Revision History Comment First Release First Release ...
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...
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... SysTick..............................................................................................................................................................................16 2.3.4 SYSRESETREQ................................................................................................................................................................16 2.3.5 LOCKUP...........................................................................................................................................................................16 2.3.6 Auxiliary Fault Status register..........................................................................................................................................16 2.4 Events......................................................................................................................................17 2.5 Power Management.................................................................................................................17 2.6 Exclusive access......................................................................................................................17 3. Debug Interface 3.1 Specification Overview...........................................................................................................19 3.2 SW-DP.....................................................................................................................................19 3.3 ETM.........................................................................................................................................19 3.4 Pin functions............................................................................................................................20 3.5 Peripheral Functions in Halt Mode.........................................................................................21 3.6 Connection with a Debug Tool...............................................................................................21 4. Memory Map 4.1 Memory Map...........................................................................................................................23 4.1.1 Memory map of the TMPM363F10FG............................................................................................................................24 4.2 SFR area detail........................................................................................................................25 i ...
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Reset 5.1 Cold reset.................................................................................................................................27 5.2 Warm reset...............................................................................................................................29 5.2.1 Reset period.......................................................................................................................................................................29 5.3 After reset................................................................................................................................29 6. Clock / Mode Control 6.1 Features....................................................................................................................................31 6.2 Registers..................................................................................................................................32 6.2.1 Register List.......................................................................................................................................................................32 6.2.2 CGSYSCR (System control register)................................................................................................................................33 6.2.3 CGOSCCR (Oscillation control register).........................................................................................................................35 6.2.4 CGSTBYCR (Standby control ...
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Exception exit 7.2 Reset Exceptions.....................................................................................................................66 7.3 Non-Maskable Interrupts (NMI).............................................................................................66 7.4 SysTick....................................................................................................................................66 7.5 Interrupts..................................................................................................................................67 7.5.1 Interrupt Sources................................................................................................................................................................67 7.5.1.1 Interrupt route 7.5.1.2 Generation 7.5.1.3 Transmission 7.5.1.4 Precautions when using external interrupt pins 7.5.1.5 List of Interrupt Sources 7.5.1.6 Active level 7.5.2 ...
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PAOD (Port A open drain control register) 8.2.1.7 PAPUP (Port A pull-up control register) 8.2.1.8 PAIE (Port A input control register) 8.2.2 Port B (PB0 to PB7)........................................................................................................................................................125 8.2.2.1 Port B Circuit Type 8.2.2.2 Port B Register 8.2.2.3 PBDATA (Port ...
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PMFR2 (Port M function register 2) 8.2.9.7 PMFR3 (Port M function register 3) 8.2.9.8 PMOD (Port M open drain control register) 8.2.9.9 PMPUP (Port M pull-up control register) 8.2.9.10 PMIE (Port M input control register) 8.2.10 Port N (PN0 ...
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Port E Setting..................................................................................................................................................................226 8.4.4 Port F Setting...................................................................................................................................................................227 8.4.5 Port G Setting..................................................................................................................................................................228 8.4.6 Port I Setting....................................................................................................................................................................229 8.4.7 Port J Setting...................................................................................................................................................................230 8.4.8 Port L Setting..................................................................................................................................................................231 8.4.9 Port M Setting.................................................................................................................................................................232 8.4.10 Port N setting.................................................................................................................................................................233 8.4.11 Port P Setting.................................................................................................................................................................234 9. DMA Controller(DMAC) 9.1 ...
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Connection example for external memory..........................................................................279 11. 16-bit Timer / Event Counters (TMRB) 11.1 Outline.................................................................................................................................281 11.2 Differences in the Specifications........................................................................................282 11.3 Configuration.......................................................................................................................284 11.4 Registers..............................................................................................................................286 11.4.1 Register list according to channel.................................................................................................................................286 11.4.2 TBxEN (Enable register)...............................................................................................................................................287 11.4.3 TBxRUN ...
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SCxTFC (TX FIFO Configuration Register) (Note2)................................................................................................330 12.4.12 SCxRST (RX FIFO Status Register)..........................................................................................................................331 12.4.13 SCxTST (TX FIFO Status Register)...........................................................................................................................332 12.5 Operation in Each Mode.....................................................................................................333 12.6 Data Format.........................................................................................................................334 12.6.1 Data Format List............................................................................................................................................................334 12.6.2 Parity Control................................................................................................................................................................335 12.6.2.1 Transmission 12.6.2.2 Receiving Data 12.6.3 ...
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Wake-up Function 12.16.4.2 Protocol 13. Synchronous Serial Port (SSP) 13.1 Overview..............................................................................................................................377 13.2 Block Diagram.....................................................................................................................378 13.3 Register................................................................................................................................379 13.3.1 Register List...................................................................................................................................................................379 13.3.2 SSPCR0(Control register 0)..........................................................................................................................................380 13.3.3 SSPCR1(Control register1)...........................................................................................................................................381 13.3.4 SSPDR(Data register)....................................................................................................................................................382 13.3.5 SSPSR(Status register)..................................................................................................................................................383 13.3.6 SSPCPSR (Clock prescale register)..............................................................................................................................384 13.3.7 SSPIMSC ...
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Interrupt Service Request and Release.........................................................................................................................415 14.5.10 Arbitration Lost Detection Monitor............................................................................................................................415 14.5.11 Slave Address Match Detection Monitor....................................................................................................................417 14.5.12 General-call Detection Monitor...................................................................................................................................417 14.5.13 Last Received Bit Monitor..........................................................................................................................................417 14.5.14 Data Buffer Register (SBIxDBR)...............................................................................................................................417 14.5.15 Baud Rate Register (SBIxBR0)..................................................................................................................................418 14.5.16 Software Reset.............................................................................................................................................................418 14.6 ...
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Detecting Error Interrupt 15.4.2.5 Details of reception error 15.4.2.6 Stopping Reception 15.4.3 Transmission..................................................................................................................................................................471 15.4.3.1 Basic Operation 15.4.3.2 Preconfiguration 15.4.3.3 Detecting Transmission Error 15.4.3.4 Details of Transmission Error 15.4.3.5 Stopping Transmission 15.4.3.6 Retransmission 15.4.4 Software Reset...............................................................................................................................................................476 16. CAN Controller 16.1 ...
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Bit Configuration.................................................................................................................526 17. Remote control signal preprocessor(RMC) 17.1 Basic operation....................................................................................................................529 17.1.1 Reception of Remote Control Signal............................................................................................................................529 17.2 Block Diagram.....................................................................................................................529 17.3 Registers..............................................................................................................................530 17.3.1 Register List...................................................................................................................................................................530 17.3.2 RMCEN(Enable Register).............................................................................................................................................531 17.3.3 RMCREN(Receive Enable Register)............................................................................................................................532 17.3.4 RMCRBUF1(Receive Data Buffer Register 1)............................................................................................................533 17.3.5 RMCRBUF2(Receive ...
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HcPeriodicStart Register.............................................................................................................................................577 18.6.18 HcLSThreshold Register.............................................................................................................................................578 18.6.19 HcRhDescriptorA Register..........................................................................................................................................579 18.6.20 HcRhDescriptorB Register..........................................................................................................................................581 18.6.21 HcRhStatus Register....................................................................................................................................................582 18.6.22 HcRhPortStatus1 Register...........................................................................................................................................583 18.6.23 HcBCR0 Register........................................................................................................................................................586 18.7 Notes on Using the USB Host Controller...........................................................................587 18.7.1 Setting the USB Clock..................................................................................................................................................587 18.7.2 Oscillator Recommendation..........................................................................................................................................587 18.7.3 Entering SLOW ...
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Backup module 21.1 Features................................................................................................................................613 21.2 Block Diagram.....................................................................................................................613 21.3 BACKUP Mode Operation.................................................................................................614 21.3.1 Operable peripherals in the BACKUP mode................................................................................................................614 21.3.1.1 Transition to the BACKUP mode 21.3.1.2 Backup Transition Flow 21.3.1.3 Transition Flowchart 21.3.1.4 BACKUP Mode Timing Chart 22. Analog / ...
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Control Register.............................................................................................................................................................652 23.3.3 Detailed Description of Control Register.....................................................................................................................654 23.3.3.1 RTCSECR (Second column register (for PAGE0 only)) 23.3.3.2 RTCMINR (Minute column register (PAGE0/1)) 23.3.3.3 RTCHOURR (Hour column register(PAGE0/1)) 23.3.3.4 RTCDAYR (Day of the week column register(PAGE0/1)) 23.3.3.5 RTCDATER (Day column ...
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ROM protection 25.1 Outline.................................................................................................................................723 25.2 Future...................................................................................................................................723 25.2.1 Write/ erase-protection function....................................................................................................................................723 25.2.2 Security function............................................................................................................................................................723 25.3 Register................................................................................................................................724 25.3.1 FCFLCS (Flash control register)...................................................................................................................................725 25.3.2 FCSECBIT(Security bit register)..................................................................................................................................726 25.4 Writing and erasing.............................................................................................................727 25.4.1 Protection bits................................................................................................................................................................727 25.4.2 Security bit.....................................................................................................................................................................727 26. RAM Interface 26.1 Register ...
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Port Section Equivalent Circuit Schematic 28.1 PA0 to 7, PB0 to 7, PP1, PP3 to 5.....................................................................................755 28.2 PE0 to 7, PF0 to 4, PG0 to 7, PI0, PL0 to 7, PM0 to 7, PN0 to 3, PP0, PP2, PP6..........755 ...
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xviii ...
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... TMPM363F10FG The TMPM363F10FG is a 32-bit RISC microprocessor series with an ARM Cortex-M3 microprocessor core. Product name TMPM363F10FG Features of the TMPM363F10FG are as follows : 1.1 Features 1. ARM Cortex-M3 microprocessor core a. Improved code efficiency has been realized through the use of Thumb-2 instruction. ・ New 16-bit Thumb instructions for improved program flow ・ ...
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... Fixed channel / scan mode ・ Single / repeat mode ・ AD monitoring 2 channels ・ Conversion speed 1.15 μsec (@ fsys = 40 MHz) 15. Key-on wake-up (KWUP channels Dynamic pull-up 16. USB host controller : 1 channel ・ Universal serial bus (Rev 2.0 standard) ・ Open HCI for USB Release 1.0a Page 2 TMPM363F10FG ...
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... On-chip PLL (Either quadrupled or octuple can be selected.) ・ Clock gear function : The high-speed clock can be divided into 1/1, 1/2, 1/4 or 1/8. 24. Endian Little endian 25. Maximum operating frequency : 64MHz (48MHz when USB is used.) 26. Operating voltage range 2 3.6 V (with on-chip regulator) 3 3.6 V (when USB is used) Page 3 TMPM363F10FG ...
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... Features 27. Temperature range ・ -40 degrees to 85 degrees (except Flash writing / erasing) ・ 0 degrees to 70 degrees (during Flash writing / erasing) 28. Package LQFP100-P-1414-0.50H ( mm, 0.5 mm pitch) Page 4 TMPM363F10FG ...
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... Block Diagram Cortex-M3 ETM SWD FLASH (1MB) RAM (40KB) Backup RAM (8KB) SMC CAN BOOT ROM Figure 1-1 TMPM363F10FG Block Diagram USB Host DMA Controller Controller NVIC AHB Lite Bus Matrix RAM0 (8KB) RAM1 (8KB) PORT A~K CG PORT WDT RTC 16bit Timer SIO/UART ...
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... Pin layout (Top view) 1.3 Pin layout (Top view) Figure 1-2 shows the pin layout of TMPM363F10FG. RVDD3 XT1 XT2 DVDD3A X1 DVSS X2 DVDD3B DVSS D+ D NMI TEST1I TEST2 PI0/BOOT Pl1/CEC AVDD3 PJ0/AIN0 PJ1/AIN1 PJ2/AIN2 PJ3/AIN3/ADTRG PJ4/AIN4/KWUP0 PJ5/AIN5/KWUP1 PJ6/AIN6/KWUP2 PJ7/AIN7/KWUP3 80 TMPM363F10FG 85 LQFP100-P-1414-0.50H 90 Top View ...
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... Pin names and Functions Table 1-1 sort input and output pins of TMPM363F10FG by pin or port. The table includes alternate pin names and function for multi-function pins. 1.4.1 Sorted by pin Table 1-1 Pin Names and Functions Sorted by Pin (1/7) Pin Input / Type PIn Name No. Output PS 1 AVSS ...
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... Receiving serial data I/O I/O port I/O Serial clock input / output Input Inputting the Timer B capture trigger Input Handshake input pin I/O I/O port Input External interrupt pin Input Inputting the Timer B capture trigger Input Inputting signal to remote controller I/O I/O port Output Chip select pin I/O I/O port Page 8 TMPM363F10FG Function ...
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... Address and data bus I/O port Address and data bus I/O port Address and data bus I/O port Address and data bus I/O port Address and data bus I/O port Address and data bus I/O port Address and data bus I/O port Address and data bus Page 9 TMPM363F10FG ...
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... CAN receiving data I/O I/O port Output Address bus I/O Serial clock input / output Input Handshake input pin I/O I/O port Input External interrupt pin Output Internal clock output pin - Power supply pin - GND pin I/O Debug pin I/O Debug pin I/O I/O port Output Debug pin Page 10 TMPM363F10FG Function ...
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... SIO mode : receive data pin Inputting the Timer B capture trigger I/O port Inputting and outputting a clock if the serial bus interface operates in the SIO mode. USB PS Chip select pin I/O port External interrupt pin USB over current Watchdog timer output pin Page 11 TMPM363F10FG ...
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... AVDD3 must be connected to power supply even if A/D converter is not used. Input Input port Input Analog input Input Input port Input Analog input Input Input port Input Analog input Input Input port Input Analog input Input External trigger input for AD converter Page 12 TMPM363F10FG Function ...
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... KWUP2 Input PJ7 Input Function 100 AIN7 Input KWUP3 Input Function Input port Analog input Key-on wake-up pin Input port Analog input Key-on wake-up pin Input port Analog input Key-on wake-up pin Input port Analog input Key-on wake-up pin Page 13 TMPM363F10FG ...
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... Pin Numbers and Power Supply Pins 1.5 Pin Numbers and Power Supply Pins Table 1-2 PIn Numbers and Power Supplies Power supply DVDD3B DVDD3A AVDD3 RVDD3 Voltage range Pin No. 33,59,83 2.7 to 3.6V 79 (When USB is used : 3.0 to 3.6V Page 14 TMPM363F10FG PIn mane PA,PB,PE,PF,PG,PI,PL,PM,PN,PP XT1,XT2,RESET,NMI,MODE X1,X2 PJ − ...
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... ARM Limited. This chapter describes the functions unique to the TX03 series that are not explained in that docu- ment. 2.1 Information on the processor core The following table shows the revision of the processor core in the TMPM363F10FG. Refer to the detailed information about the CPU core and architecture, refer to the ARM manual "Cortex-M ser- ies processors" in the following URL : http://infocenter.arm.com/help/index.jsp 2 ...
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... SysTick The Cortex-M3 core has a SysTick timer which can generate SysTick exception. In the TMPM363F10FG, the clock that is input from X1 pin dividing used as a count clock for the Systic timer. SysTick calibration register can set a calibration value to measure 10ms. In this product, when 8MHz is input to X1 pin, calibration value is set to 0x9C4 which can measure 10ms. Additionally, if this value is read as " ...
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... The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV in- struction execution event is input, the core returns from low-power consumption mode caused by WFE instruc- tion. TMPM363F10FG does not use event output signals and event input signals. Please do not use SEV instruction and WFE instruction. 2.5 ...
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... Exclusive access Page 18 TMPM363F10FG ...
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... Debug Interface 3.1 Specification Overview The TMPM363F10FG contains the Serial Wire Debug Port (SW-DP) unit for interfacing with the debugging tools and the Embedded Trace Macrocell ted pins (TRACEDATA[3:0]) via the on-chip Trace Port Interface Unit (TPIU). For details about SW-DP, ETM and TPIU, refer to "Cortex-M3 Technical Reference Manual". ...
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... TRACEDATA1 0 0 TRACEDATA2 0 0 TRACEDATA3 0 0 Page 20 TMPM363F10FG SW debug function Comments Serial Wire Data Input/Output (Always pull-up) Serial Wire Clock (Always pull-down) TRACE Clock Output TRACE DATA Output0 / Serial Wire Viewer Output TRACE DATA Output1 TRACE DATA Output2 TRACE DATA Output3 ...
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... Connection with a Debug Tool Concerning a connection with debug tools, refer to manufactures recommendations. Debug interface pins contain a pull-up resistor and a pull-down resistor.When debug interface pins are connec- ted with external pull-up or pull-down, please pay attention to input level. Page 21 TMPM363F10FG ...
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... Connection with a Debug Tool Page 22 TMPM363F10FG ...
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... Memory Map The memory maps for the TMPM363F10FG are based on the ARM Cortex-M3 processor core memory map. The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped to the SRAM region and the special function register (SFR) is mapped to the peripheral region respectively. ...
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... Memory Map 4.1.1 Memory map of the TMPM363F10FG Figure 4-1 shows the memory map of the TMPM363F10FG. Vender-Specific CPU Register Region Fault External Bus Area Fault SFR Fault SFR Fault SFR Fault SFR Fault Backup RAM (8K) Internal RAM (56K) Fault Internal ROM (1024K) Figure 4-1 Memory map ...
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... RTC 0x400F_300D 0x400F_4028 to CG 0x400F_4036 to 0x41FF_F000 to 0x41FF_F014 to FLASH 0x41FF_F018 to 0x41FF_F024 to 0x41FF_F033 to Reserved RAMWAIT Reserved Reserved SMCMOD Page 25 TMPM363F10FG 0x4000_002F 0x4000_0037 0x4000_050F 0x4000_0FFF 0x4000_1003 0x4000_100F 0x4000_1023 0x4000_1207 0x4000_1E0B 0x4000_1FFF 0x4000_305F 0x4004_0FFF 0x400C_03FF 0x400C_07FF 0x400C_0AFF 0x400C_0EFF 0x400E_041F 0x400E_1BFF 0x400E_313F 0x400F_001F 0x400F_002F 0x400F_107F 0x400F_402F ...
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... SFR area detail Page 26 TMPM363F10FG ...
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... Reset The TMPM363F10FG has three reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the setting <SYSRESETREQ> in the Application Interrupt and Reset Control Register. For reset from the WDT, refer to the chapter on the WDT. For reset from <SYSRESETREQ>, refer to "Cortex-M3 Technical Reference Manual". ...
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... Cold reset Note 1: The power supply must be raised (from 0V to 2.7V speed of 0.1ms/V or slower. Note 2: Turn on the power while the RESET pin is fixed to "Low". When all the power supplies are stabilized within operating volt- age, release the reset. Page 28 TMPM363F10FG ...
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... As a precondition, ensure that the power supply voltage is within the operating range and the internal high- frequency oscillator is providing stable oscillation. To reset the TMPM363F10FG, assert the RESET signal (active low) for a minimum duration of 12 system clocks. After the external reset (RESET) signal is released, the internal reset signal remains asserted for a further 400μ ...
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... After reset Page 30 TMPM363F10FG ...
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... Controls the system clock ・ Controls the prescaler clock ・ Controls the PLL multiplication circuit ・ Controls the warm-up timer In addition to NORMAL mode, the TMPM363F10FG can operate in six types of low power mode to reduce pow- er consumption according to its usage conditions. Page 31 TMPM363F10FG ...
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... The following table shows the CG-related registers and addresses. System control register Oscillation control register Standby control register PLL selection register System clock selection register Register name CGSYSCR CGOSCCR CGSTBYCR CGPLLSEL CGCKSEL Page 32 TMPM363F10FG Base Address = 0x400F_4000 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 ...
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... Reserved Specifies the prescaler clock to peripheral I/O. 7-3 − R Read as "0" FCSTOP - FPSEL1 FPSEL0 - Function Page 33 TMPM363F10FG SCOSEL PRCK GEAR ...
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... Registers Bit Bit Symbol Type 2-0 GEAR[2:0] R/W High-speed clock (fc) gear 000: fc 001: Reserved 010: Reserved 011: Reserved 100: fc/2 101: fc/4 110: fc/8 111: Reserved Page 34 TMPM363F10FG Function ...
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... Starting warm-up Enables to start the warm-up timer WUPT WUPSEL PLLON Function Page 35 TMPM363F10FG XTEN XEN WUEF WUEON ...
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... High-speed oscillator operation after releasing the STOP mode. 0: Stop 1: Oscillation Read as "0". Low power consumption mode 000: Reserved 001: STOP 010: SLEEP 011: IDLE2 100: Reserved 101: BACKUP STOP 110: BACKUP SLEEP 111: IDLE1 Page 36 TMPM363F10FG ...
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... Resetting is required when using the PLL Function Page 37 TMPM363F10FG C2S PLLSEL ...
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... Setting CGOSCCR<XEN> and <XTEN> to "1" in advance is required. System clock status 0: High-speed (fc) 1: Low-speed (fs) Shows the status of the system clock. Switching the oscillator with <SYSCK> generates time lag to complete. If the output of the oscillator specified in <SYSCK> is read out by <SYSCLKFLG>, the switching has been completed. Page 38 TMPM363F10FG ...
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... Reset operation causes all the clock configurations excluding the low-speed clock (fs the same as fosc fosc fsys = fosc φT0 = fosc For example, reset operation configures fsys as 10MHz when a 10MHz oscillator is connected to the pin. : fc, fc/2, fc/4, fc/8 : fs, fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32 : fsys : fosc/32 : oscillating : oscillating : stop : fc (no frequency dividing) Page 39 TMPM363F10FG ...
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... CGOSCCR<PLLON> Stops after releasing reset fs 1/32 CGSYSCR <FPSEL1> CGSYSCR 1/2 1/4 1/8 1/16 1/32 <PRCK[2:0]> 1/2 Figure 6-1 Clock Block Diagram Page 40 TMPM363F10FG ADC conversion FCSTOP clock <ADCLK> CGSYSCR<FPSEL0> fperiph ( I/O ) fgear fsys 1/8 CGSYSCR CGCKSEL <GEAR[2:0]> <SYSCK> fs Systick Timer input CPU(STCLK) φT0 ...
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... CGOSCCR <PLLON> = “0” (PLL stop) must be retained 100μs or more for stablization. By setting CGOSCCR<PLLON>=” 1”→“0” (PLL stop), multiplier factor will be initialized to “4” . Starting PLL operation needs to approximately 200μs or more stablization time by retaining CGOSCCR<PLLON>= “1” (PLL on). Page 41 TMPM363F10FG ...
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... It takes 100μs or more for the PLL to be stabilized when changed PLL setting to hole the CGOSCCR<PLLON>= “0” (PLL stop) It takes approx 200μs for the PLL to be stabilized. To hold the CGOSCCR<PLLON>=” 1” (PLL active). Figure 6-3 Changing the PLL setting Page 42 TMPM363F10FG Note ...
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... Check warm-up counter setting : Enable high-speed oscillation (fosc) : Enable warm-up counting (WUP) : Wait for "0" (end of WUP) : system clock changed to high-speed (fgear) : Wait for "0" (the current clock is fgear) : Disable the low-speed oscillation (fs) (In dual clock mode, it’s not required.) Page 43 TMPM363F10FG ...
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... Enable low-speed oscillation (fs) : Select XT1 for warm-up clock : Enable warm-up counting (WUP) : Wait for "0" (end of WUP) : system clock changed to low-speed (fs) : Wait for "1" (the current clock is fs) : Disable the high-speed oscillation (fc) (In dual clock mode, it’s not required.) Page 44 TMPM363F10FG ...
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... System Clock The TMPM363F10FG offers two selectable system clocks: low-speed or high-speed. The high-speed clock is dividable. Note 1: Switching of clock gear is executed when a value is written to the CGSYSCR<GEAR[2:0]> register. The ac- tual switching takes place after a slight delay. Note 2: When PLL is used as octuple, do not use the oscillator which is upper than 8MHz. ...
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... System Clock Pin Output Function TMPM363F10FG enables to output the system clock from a pin. The SCOUT pin can output the low speed clock fs, the system clock fsys and fsys/2, and the prescaler input clock for peripheral I/O φT0. The out- put clock is selected by setting the CGSYSCR<SCOSEL[1:0]>. ...
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... When the low-speed clock is not used, the SLOW and SLEEP modes cannot be used. Also, TMPM363F10FG has a BACKUP mode. This mode can reduce power consumption of full width by shutdown main power supply of almost function except particular one. ...
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... Note 1: Be sure to stop peripheral functions except for the CPU, TMRB, RTC, I/O ports, CEC, RMC and KWUP be- fore switching to the SLOW mode. Note 2: In the SLOW mode, be sure not to perform reset using the Application Interrupt and Reset Control Regis- ter <SYSRESETREQ> of the Cortex-M3 NVIC register. Page 48 TMPM363F10FG ...
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... Releasing by the interrupt requires settings in advance. See the chapter "Exceptions" for details. Note 1: The TMPM363F10FG does not offer any event for releasing the low power consumption mode. Transition to the low power consumption mode by executing the WFE (Wait For Event) instruction is prohibited. ...
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... Pin name I/O Input only Output only Input only Input Output Input Output Input Output Input Output Input Output Page 50 TMPM363F10FG <DRVE> <DRVE> × × "High" level output "High" level output ο ο ο ο × Depends on (PxCR[m]) ο ο × Depends on (PxCR[m]) × ...
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... Table 6-6 shows the mode setting in the <STBY[2:0]>. Table 6-6 Low power consumption mode setting Mode Reserved STOP SLEEP IDLE2 Reserved BACKUP STOP BACKUP SLEEP IDLE1 Note:Do not use reserved mode setting. CGSTBYCR <STBY[2:0]> 000 001 010 011 100 101 110 111 Page 51 TMPM363F10FG ...
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... Page 52 TMPM363F10FG BACKUP SLEEP STOP SLEEP − − × − − × ο ο × − − × ο (note 6) ο (note 2) Δ (note 3) Δ ...
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... Releasing the Low Power Consumption Mode The low power consumption mode can be released by an interrupt request, Non-Maskable Interrupt (NMI) or reset. The release source that can be used is determined by the low power consumption mode selected. Details are shown in Table 6-8. Page 53 TMPM363F10FG ...
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... Page 54 TMPM363F10FG BACKUP BACKUP SLEEP STOP (note 2) (note 2) ο ο × × × × × × × × × × × × ...
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... Auto-warm-up (note 3) High-speed oscillator : more than 100μs Auto-warm-up High-speed oscillator : Setting value of warm-up time Not required Auto-warm-up High-speed oscillator : Setting value of warm-up time Auto-warm-up Low-speed oscillator :Setting value of warm-up time Auto-warm-up (note 3) High-speed oscillator : more than 500μs Page 55 TMPM363F10FG ...
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... Table 6-9 Warm-up setting in mode transition Mode transition Warm-up setting Auto-warm-up (note 3) BACKUP STOP → NORMAL High-speed oscillator : more than Auto-warm-up (note 3) BACKUP SLEEP → SLOW Low-speed oscillator : more than Auto-warm-up (note 3) BACKUP STOP → SLOW Low-speed oscillator : more than Page 56 TMPM363F10FG 500μs 2.5ms 2.5ms ...
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... System clock stops Release event occurs STOP High-speed clock starts oscillating Warm-up completes. Warm-up starts System clock starts. Release event occurs SLEEP Oscillation continues High-speed clock starts oscillating Warm-up completes. Warm-up starts System clock starts. Page 57 TMPM363F10FG NORMAL NORMAL ...
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... WFI excute/ sleep on exit Release event occurs STOP System clock stops Low-speed clock starts oscillating Warm-up starts WFI excute/ sleep on exit SLEEP System clock stops Page 58 TMPM363F10FG SLOW Warm-up completes System clock starts Release event occurs SLOW System clock starts ...
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... For detailed descriptions on each exception, refer to "Cortex-M3 Technical Reference Manual". ・ Reset ・ Non-Maskable Interrupt (NMI) ・ Hard Fault ・ Memory Management ・ Bus Fault ・ Usage Fault ・ SVCall (Supervisor Call) ・ Debug Monitor ・ PendSV ・ SysTick ・ External Interrupt Page 59 TMPM363F10FG ...
Page 86
... Description The CG/CPU detects the exception request. The CPU handles the exception request. The CPU branches to the corresponding interrupt service routine (ISR). Necessary processing is executed. The CPU branches to another ISR or returns to the previous program. Page 60 TMPM363F10FG See Section 7.1.2.1 Section 7.1.2.2 Section 7.1.2.4 Section 7.1.2.4 ...
Page 87
... Access violation to the Hard Fault region of the memory map Undefined instruction execution or other faults related to instruction ex- ecution System service call with SVC instruction Debug monitor when the CPU is not faulting Pendable system service request Notification from system timer External interrupt pin or peripheral function (Note2) Page 61 TMPM363F10FG ...
Page 88
... Pre-emption Subpriority field field [7:1] [0] [7:2] [1:0] [7:3] [2:0] [7:4] [3:0] [7:5] [4:0] [7:6] [5:0] [7] [6:0] None [7:0] ple, in the case of 3-bit configuration, the priority is set as <PRI_n[7:5]> and <PRI_n[4:0] > is "00000". Page 62 TMPM363F10FG Number of Number of pre-emption subpriorities priorities 128 128 1 256 ...
Page 89
... A late-arriving exception causes the CPU to fetch a new vector address for branching to the corre- sponding ISR, but the CPU does not newly push the register contents to the stack. (4) Vector table The vector table is configured as shown below. Old SP → <previous> xPSR PC LR r12 → r0 Page 63 TMPM363F10FG ...
Page 90
... Bus Fault ISR address Usage Fault ISR address Reserved SVCall ISR address Debug Monitor ISR address Reserved PendSV ISR address SysTick ISR address External Interrupt ISR address Page 64 TMPM363F10FG Setting Required Required Required Required Optional Optional Optional Optional Optional Optional Optional Optional ...
Page 91
... Load current active interrupt number Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which interrupt to return to. ・ Select SP If returning to an exception (Handler Mode SP_main. If returning to Thread Mode, SP can be SP_main or SP_process. Page 65 TMPM363F10FG ...
Page 92
... Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32.The SysTick Calibration Value Register is set to 0x9C4, which provides 10 ms tim- ing when the clock input from MHz. Page 66 TMPM363F10FG ...
Page 93
... External Port interrupt pin Peripheral function 7.5.1.2 Generation An interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the NVIC's Interrupt Set-Pending Register. Interrupt request <INTxEN> Exiting standby mode Clock generator Figure 7-1 Interrupt Route Page 67 TMPM363F10FG CPU ...
Page 94
... Set the port control register so that the external pin can perform as an interrupt function pin. Set the peripheral function to make it possible to output interrupt requests. See the chapter of each peripheral function for details. An interrupt request can be generated by setting the relevant bit of the Interrupt Set-Pend- Page 68 TMPM363F10FG ...
Page 95
... AD conversion monitoring function interrupt 1 40 INTTB0 16-bit TMRB match detection 0 41 INTTB1 16-bit TMRB match detection 1 42 INTTB2 16-bit TMRB match detection 2 active level (Clearing standby) Selectable - Rising edge - Falling edge High level Page 69 TMPM363F10FG CG interrupt mode control register CGIMCGA CGIMCGB - CGIMCGE - CGIMCGF ...
Page 96
... TMRB input capture 50 16-bit TMRB input capture 51 16-bit TMRB input capture 60 16-bit TMRB input capture 61 16-bit TMRB input capture 70 16-bit TMRB input capture 71 16-bit TMRB input capture 90 16-bit TMRB input capture 91 Page 70 TMPM363F10FG active level CG interrupt mode (Clearing standby) control register ...
Page 97
... Note:For the CEC reception / transmission, remote control signal reception and real time clock in- terrupts, set the <INTxEN> bit to "1" and specify the active level, even when they are not used for clearing a standby mode. active level (Clearing standby) Page 71 TMPM363F10FG CG interrupt mode control register ...
Page 98
... If multiple interrupt requests occur simultaneously, the interrupt request with the highest priority is detected according to the priority order. The CPU handles the interrupt. The CPU pushes register contents to the stack before entering the ISR. Page 72 TMPM363F10FG See "7.5.2.2 Preparation" "7.5.2.3 Detection by Clock Generator" ...
Page 99
... Processing Program for the ISR. ISR execution Clear the interrupt source if needed. Return to preceding Configure to return to the preceding program of the ISR. program Details Page 73 TMPM363F10FG See "7.5.2.6 Interrupt Serv- ice Routine (ISR)" ...
Page 100
... Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but the number of bits actually used varies with each product.Priority level 0 is the highest priority lev- el.If multiple sources have the same priority, the smallest-numbered interrupt source has the highest priority. ← "1"(Interrupt disabled) Page 74 TMPM363F10FG ...
Page 101
... Before enabling an interrupt, clear the corresponding interrupt request already held. This can avoid unexpected interrupt.To clear corresponding interrupt request, write a value corresponding to the interrupt to be used to the CGICRCG register.See "7.6.3.5 CGICRCG (CG Interrupt Request Clear Register)" for each value. Page 75 TMPM363F10FG ...
Page 102
... If a standby mode is exited without clearing the interrupt request, the same interrupt will be detected again when normal operation is resumed. Be sure to clear each interrupt request in the ISR. ← active level ← Value corresponding to the interrupt to be used ← "1" (interrupt enabled) ← "1" ← "1" ← "0" Page 76 TMPM363F10FG ...
Page 103
... Therefore, the interrupt source must be cleared. Clearing the interrupt source au- tomatically clears the interrupt request signal from the clock generator interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding val the CGICRCG register. When an active edge occurs again, a new interrupt request will be detec- ted. Page 77 TMPM363F10FG ...
Page 104
... CG Interrupt Mode Control Register F Reserved Reserved Note:Access to the "Reserved" areas is prohibited. Register name Register name CGICRCG CGNMIFLG CGRSTFLG CGIMCGA CGIMCGB - CGIMCGD CGIMCGE CGIMCGF - - Page 78 TMPM363F10FG Base Address = 0xE000_E000 Address 0x0010 0x0014 0x0018 0x001C 0x0100 0x0104 0x0108 0x010C 0x0180 0x0184 0x0188 0x018C 0x0200 0x0204 0x0208 ...
Page 105
... If "1" is set, it reloads with the value of the Reload Value Register and starts operation CLKSOURCE Function Page 79 TMPM363F10FG COUNTFLAG TICKINT ENABLE ...
Page 106
... Undefined CURRENT Undefined Read as 0. [Read] Current SysTick timer value [Write] Clear Writing to this register with any value clears Clearing this register also clears the <COUNTFLAG> bit of the SysTick Control and Status Register. Page 80 TMPM363F10FG ...
Page 107
... SysTick Calibration Value Register is set to a value that provides 10 ms timing when the cock input from MHz TENMS TENMS TENMS Function Page 81 TMPM363F10FG ...
Page 108
... Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 82 TMPM363F10FG SETENA SETENA ...
Page 109
... SETENA SETENA SETENA (Interrupt 44) (Interrupt 43) (Interrupt 42 SETENA SETENA - (Interrupt 35) (Interrupt 34 Function Page 83 TMPM363F10FG SETENA SETENA SETENA (Interrupt 57) (Interrupt 56 SETENA SETENA SETENA (Interrupt 49) (Interrupt 48 SETENA SETENA SETENA ...
Page 110
... Reading the bits can see the enable/disable condition of the corresponding interrupts. Write Page 84 TMPM363F10FG SETENA SETENA SETENA (Interrupt 83) (Interrupt 82) (Interrupt 81 SETENA SETENA - (Interrupt 75) (Interrupt 74 ...
Page 111
... Writing "1" bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 1-0 − R/W Write as 0. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Function Page 85 TMPM363F10FG ...
Page 112
... Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 86 TMPM363F10FG CLRENA ...
Page 113
... CLRENA CLRENA CLRENA (Interrupt 44) (Interrupt 43) (Interrupt 42 CLRENA CLRENA - (Interrupt 35) (Interrupt 34 Function Page 87 TMPM363F10FG CLRENA CLRENA CLRENA (Interrupt 57) (Interrupt 56 CLRENA CLRENA CLRENA (Interrupt 49) (Interrupt 48 CLRENA CLRENA CLRENA ...
Page 114
... Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Write as 0. Page 88 TMPM363F10FG ...
Page 115
... Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" CLRENA CLRENA - - (Interrupt 99) (Interrupt 98 Function Page 89 TMPM363F10FG ...
Page 116
... Writing "1" bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Page 90 TMPM363F10FG SETPEND ...
Page 117
... Undefined Undefined Undefined SETPEND SETPEND (Interrupt 44) (Interrupt 43) (Interrupt 42) Undefined Undefined Undefined SETPEND - (Interrupt 35) (Interrupt 34) Undefined Undefined Undefined Function Page 91 TMPM363F10FG SETPEND SETPEND SETPEND (Interrupt 57) (Interrupt 56) Undefined Undefined Undefined SETPEND SETPEND SETPEND (Interrupt 49) (Interrupt 48) Undefined Undefined Undefined ...
Page 118
... Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Write as 0. Page 92 TMPM363F10FG ...
Page 119
... Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" SETPEND SETPEND - - (Interrupt 99) (Interrupt 98 Undefined Undefined Function Page 93 TMPM363F10FG Undefined Undefined ...
Page 120
... Writing "1" bit in this register clears the corresponding pending interrupt. However, writing "1" has no ef- fect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Page 94 TMPM363F10FG ...
Page 121
... Undefined CLRPEND CLRPEND CLRPEND (Interrupt 44) (Interrupt 43) (Interrupt 42) Undefined Undefined Undefined CLRPEND CLRPEND - (Interrupt 35) (Interrupt 34) Undefined Undefined Undefined Function Page 95 TMPM363F10FG CLRPEND CLRPEND (Interrupt 57) (Interrupt 56) Undefined Undefined Undefined CLRPEND CLRPEND (Interrupt 49) (Interrupt 48) Undefined Undefined Undefined CLRPEND CLRPEND ...
Page 122
... Writing "1" bit in this register clears the corresponding pending interrupt. However, writing "1" has no ef- fect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Write as 0. Page 96 TMPM363F10FG ...
Page 123
... Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" CLRPEND CLRPEND - - (Interrupt 99) (Interrupt 98 Undefined Undefined Function Page 97 TMPM363F10FG Undefined Undefined ...
Page 124
... PRI_75 PRI_74 PRI_79 PRI_78 PRI_83 PRI_82 PRI_87 PRI_86 − − − − PRI_99 PRI_98 Page 98 TMPM363F10FG PRI_1 PRI_0 PRI_5 PRI_4 − − − − PRI_17 PRI_16 PRI_21 PRI_20 PRI_25 PRI_24 PRI_29 PRI_28 PRI_33 PRI_32 PRI_37 − ...
Page 125
... Function Page 99 TMPM363F10FG − − − − − − − − − − ...
Page 126
... The offset must be aligned based on the number of exceptions in the table.This means that the minimum alignment is 32 words that you can use for interrupts.For more interrupts, you must adjust the align- ment by rounding up to the next power of two. Read as 0, Page 100 TMPM363F10FG TBLOFF ...
Page 127
... Note 2: When SYSRESETREQ is output, warm reset is performed on this product. <SYSRESETREQ> is cleared by warm reset VECTKEY/VECTKEYSTAT VECTKEY/VECTKEYSTAT SYSRESET - - - REQ Function Page 101 TMPM363F10FG PRIGROUP VECTCLR VECTRESET ACTIVE ...
Page 128
... PRI_4 - Reserved Read as 0, Priority of Usage Fault Read as 0, Priority of Bus Fault Read as 0, Priority of Memory Management Read as 0, Page 102 TMPM363F10FG PRI_5 PRI_4 (Bus Fault) (Memory Management) PRI_9 PRI_8 PRI_13 PRI_12 (Debug Monitor ...
Page 129
... USGFAULT - - - USGFAULT SYSTICKACT PENDSVACT PENDED PENDED USGFAULT - - ACT Function Page 103 TMPM363F10FG BUSFAULT MEMFAULT ENA ENA ENA MONITOR - ACT BUSFAULT MEMFAULT - ...
Page 130
... MEMFAULT R/W ACT Note:You must clear or set the active bits with extreme caution because clearing and setting these bits does not re- pair stack contents. Usage Fault 0: Inactive 1: Active Read as 0, Bus Fault 0: Inactive 1: Active Memory management 0: Inactive 1: Active Page 104 TMPM363F10FG Function ...
Page 131
... R Read EMCG3 EMST3 EMCG2 EMST2 EMCG1 EMST1 EMCG0 EMST0 Function Page 105 TMPM363F10FG INT3EN 0 Undefined INT2EN 0 Undefined INT1EN 0 Undefined INT0EN 0 Undefined 0 ...
Page 132
... INT0 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge active level of INT0 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge Reads as undefined. INT0 clear input 0: Disable 1: Enable Page 106 TMPM363F10FG Function ...
Page 133
... Both edge EMCG7 EMST7 EMCG6 EMST6 EMCG5 EMST5 EMCG4 EMST4 Function Page 107 TMPM363F10FG INT7EN 0 Undefined INT6EN 0 Undefined INT5EN 0 Undefined INT4EN 0 Undefined 0 ...
Page 134
... INT4 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge active level of INT4 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge Reads as undefined. INT4 clear input 0: Disable 1: Enable Page 108 TMPM363F10FG Function ...
Page 135
... Set it as shown below. 011: Rising edge EMCGI EMSTI EMCGH EMSTH EMCGG EMSTG Function Page 109 TMPM363F10FG Undefined INTIEN 0 Undefined INTHEN 0 Undefined INTGEN 0 Undefined 0 ...
Page 136
... Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is pro- hibited. active level of INTCECRX standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edge Read as undefined. INTCECRX Clear input 0:Disable 1: Enable Page 110 TMPM363F10FG Function ...
Page 137
... Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is pro- hibited EMCGL EMSTL EMCGK EMSTK Function Page 111 TMPM363F10FG INTLEN 0 Undefined INTKEN 0 Undefined 0 ...
Page 138
... INT0 0_1000: Reserved 0_0001: INT1 0_1001: Reserved 0_0010: INT2 0_1010: Reserved 0_0011: INT3 0_1011: Reserved 0_0100: INT4 0_1100: Reserved 0_0101: INT5 0_1101: Reserved 0_0110: INT6 0_1110: Reserved 0_ 0111: INT7 0_1111: Reserved Read as 0. Page 112 TMPM363F10FG ...
Page 139
... WDT Note:<NMIFLG> are cleared to "0" when they are read Function Page 113 TMPM363F10FG NMIFLG1 NMIFLG0 ...
Page 140
... Reset from BACKUP mode release WDT reset flag 0: "0" is written 1: Reset from WDT RESET pin flag 0: "0" is written 1: Reset from RESET pin Power-on flag 0: "0" is written 1: Reset from power-on reset Page 114 TMPM363F10FG ...
Page 141
... Input / Output Ports 8.1 Port Functions 8.1.1 Function list TMPM363F10FG has 74 ports. Besides the ports function, these ports can be used as I/O pins for peripher- al functions. Table 8-1 shows the port function table. Table 8-1 Port Function List Input / Port PIn Output Port A PA0 I/O PA1 I/O PA2 I/O PA3 ...
Page 142
... Pull-up ο − I/O Pull-up ο − I/O Pull-up ο ο I/O Pull-up ο − Page 116 TMPM363F10FG Program- mable Function pin Open-drain ο SDA1/ SO1 , TB7IN0 ο SCL1/ SI1 , TB7IN1 ο SCK1 , CS0 ο INT6 , CS1 ο SDA2/ SO2 , TB9IN0 ο SCL2/ SI2 , TB9IN1 ο ...
Page 143
... Note 3: N-ch open drain port Program- Schmitt Noise mable Function pin Input Filter Open-drain − − ο − ο − ο BLS0 , SPDO − − ο BLS1 , SPDI − − ο SPCLK − − ο SPFSS ο − ο ALE Page 117 TMPM363F10FG ...
Page 144
... When PxOD is set "1",output buffer is disabled and pseudo-open-drain is materialized. ・ PxPUP: Port x pull-up control register To control programmable pull ups. ・ PxPDN: Port x pull-down control register To control programmable pull downs. ・ PxIE : Port x input control register To control inputs. For avoided through current, default setting prohibits inputs. Page 118 TMPM363F10FG ...
Page 145
... Output × Input ο Output × Input × Output Depend on PxCR[m] Input ο Output Depend on PxCR[m] Input × Output × Page 119 TMPM363F10FG <DRVE> × "High"Level Output ο ο Depend on PxCR[m] ο Depend on PxCR[m] Depend on PxCR[m] ο Depend on PxCR[m] Depend on PxCR[m] ...
Page 146
... Port A open drain control register Port A pull-up control register Port A input control register Register name PADATA PACR PAFR1 PAOD PAPUP PAIE Page 120 TMPM363F10FG Base Address = 0x400C_0000 Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 0 T1 ...
Page 147
... PA5 PA4 PA3 Function PA5C PA4C PA3C Function Page 121 TMPM363F10FG PA2 PA1 PA0 ...
Page 148
... PA6F1 PA5F1 PA4F1 Read PORT 1 : D7, AD7 0: PORT 1: D6, AD6 0: PORT 1: D5, AD5 0: PORT 1: D4, AD4 0: PORT 1: D3, AD3 0: PORT 1: D2, AD2 0: PORT 1: D1, AD1 0: PORT 1: D0, AD0 Page 122 TMPM363F10FG ...
Page 149
... PA5OD PA4OD PA3OD Function PA5UP PA4UP PA3UP Function Page 123 TMPM363F10FG PA2OD PA1OD PA0OD ...
Page 150
... PA7IE to PA0IE R PA6IE PA5IE PA4IE Read as 0. Input 0: Disable 1: Enable Page 124 TMPM363F10FG PA3IE PA2IE PA1IE Function ...
Page 151
... Port B function register 1 Port B open drain control register Port B pull-up control register Port B input control register Base Address = 0x400C_0100 PBDATA PBCR PBFR1 PBOD PBPUP PBIE Page 125 TMPM363F10FG Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 ...
Page 152
... Port B data register PB6C PB5C PB4C Read as 0. Output 0: Disable 1: Enable Page 126 TMPM363F10FG PB3 PB2 PB1 Function ...
Page 153
... D10, AD10 1 PB1F1 R/W 0: PORT 1: D9, AD9 0 PB0F1 R/W 0: PORT 1: D8, AD8 PB5F1 PB4F1 PB3F1 Function Page 127 TMPM363F10FG PB2F1 PB1F1 PB0F1 ...
Page 154
... CMOS 1 : Open-drain PB6UP PB5UP PB4UP Read as 0. Pull-up 0: Disable 1: Enable Page 128 TMPM363F10FG PB3OD PB2OD PB1OD Function ...
Page 155
... Type 31-8 − R Read as 0. 7-0 PB7IE to PB0IE R/W Input 0: Disable 1: Enable PB5IE PB4IE PB3IE Function Page 129 TMPM363F10FG PB2IE PB1IE PB0IE ...
Page 156
... Port E pull-up control register Port E input control register T37 T36 Register name PEDATA PECR PEFR1 PEFR2 PEFR3 PEOD PEPUP PEIE Page 130 TMPM363F10FG Base Address = 0x400C_0400 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 0 ...
Page 157
... PE5 PE4 PE3 Function PE5C PE4C PE3C Function Page 131 TMPM363F10FG PE2 PE1 PE0 ...
Page 158
... PE6F1 PE5F1 PE4F1 Read as 0. Write "0". 0: PORT 1:A23 0: PORT 1: A22 0: PORT 1: A21 0: PORT 1: A20 0: PORT 1: A19 0: PORT 1: A18 0: PORT 1: A17 Page 132 TMPM363F10FG PE3F1 ...
Page 159
... PE2F2 R/W 0: PORT 1: TB6IN0 1 PE1F2 R/W 0: PORT 1: TB5IN1 0 PE0F2 R/W 0: PORT 1: TB5IN0 PE5F2 PE4F2 PE3F2 Function Page 133 TMPM363F10FG PE2F2 PE1F2 PE0F2 ...
Page 160
... CRXD 0 : PORT 1 : CTXD Read PE6OD PE5OD PE4OD Read CMOS 1 : Open-drain Page 134 TMPM363F10FG Function ...
Page 161
... PE5UP PE4UP PE3UP Function PE5IE PE4IE PE3IE Function Page 135 TMPM363F10FG PE2UP PE1UP PE0UP ...
Page 162
... Port F open drain control register Port F pull-up control register Port F input control register − − T7 Register name PFDATA PFCR PFFR1 PFOD PFPUP PFIE Page 136 TMPM363F10FG Base Address = 0x400C_0500 Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 0 T7 ...
Page 163
... PF4 PF3 PF2 Function PF4C PF3C PF2C Function Page 137 TMPM363F10FG PF1 PF0 ...
Page 164
... PF4F1 Read PORT 1: TRACEDATA3 0: PORT 1: TRACEDATA2 0: PORT 1: TRACEDATA1 0: PORT 1: TRACEDATA0 / SWV 0: PORT 1: TRACECLK Page 138 TMPM363F10FG PF3F1 PF2F1 PF1F1 Function 24 - ...
Page 165
... PF4OD PF3OD PF2OD Function PF4UP PF3UP PF2UP Function Page 139 TMPM363F10FG PF1OD PF0OD ...
Page 166
... R 4-0 PF4IE to PF0IE R PF4IE Read as 0. Input 0: Disable 1: Enable Page 140 TMPM363F10FG PF3IE PF2IE PF1IE Function ...
Page 167
... Port G open drain control register Port G pull-up control register Port G input control register T10 T9 Base Address = 0x400C_0600 PGDATA PGCR PGFR1 PGFR2 PGFR3 PGOD PGPUP PGIE Page 141 TMPM363F10FG Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 ...
Page 168
... Port G data register PG6C PG5C PG4C Read as 0. Output 0: Disable 1: Enable Page 142 TMPM363F10FG PG3 PG2 PG1 Function ...
Page 169
... SCK1 1 PG1F1 R/W 0: PORT 1: SCL1 / SI1 0 PG0F1 R/W 0: PORT 1: SDA1 / SO1 PG5F1 PG4F1 PG3F1 Function Page 143 TMPM363F10FG PG2F1 PG1F1 PG0F1 ...
Page 170
... PG6F2 PG5F2 PG4F2 Read PORT 1 : USBOC 0 : PORT 1 : USBPON 0: PORT 1: TB9IN1 0: PORT 1: TB9IN0 Read PORT 1: TB7IN1 0: PORT 1: TB7IN0 Page 144 TMPM363F10FG PG1F2 PG0F2 0 ...
Page 171
... R Read PG3F3 R PORT 1 : CS1 2 PG2F3 R PORT 1 : CS0 − R Read PG3F3 PG2F3 Function Page 145 TMPM363F10FG ...
Page 172
... CMOS 1 : Open-drain PG6UP PG5UP PG4UP Read as 0. Pull-up 0: Disable 1: Enable Page 146 TMPM363F10FG PG3OD PG2OD PG1OD Function ...
Page 173
... Type 31-8 − R Read as 0. 7-0 PG7IE to R/W Input PG0IE 0: Disable 1: Enable PG5IE PG4IE PG3IE Function Page 147 TMPM363F10FG PG2IE PG1IE PG0IE ...
Page 174
... Port I open drain control register Port I pull-up control register Port I input control register − − − Register name PIDATA PICR PIFR1 PIOD PIPUP PIIE Page 148 TMPM363F10FG − − T15 T14 Base Address = 0x400C_0800 Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 0 ...
Page 175
... R Read as 0. 3-2 − R/W Write "0". 1-0 PI1 to PI0 R/W Port I data register Function Page 149 TMPM363F10FG PI1 PI0 ...
Page 176
... R/W 1-0 PI1C-PI0C R Read as 0. Write "0". Output 0: Disable 1: Enable Page 150 TMPM363F10FG PI1C Function ...
Page 177
... R Read as 0. 3-2 − R/W Write "0". 1 PI1F1 R/W 0: PORT 1: CEC 0 − R/W Write Function Page 151 TMPM363F10FG PI1F1 - ...
Page 178
... Write "0". Read CMOS 1 : Open-drain Read as 0. Pull-up 0: Disable 1: Enable Page 152 TMPM363F10FG Function ...
Page 179
... Type 31-4 − R Read as 0. 3-2 − R/W Write "0". 1-0 PI1IE-PI0IE R/W Input 0: Disable 1: Enable Function Page 153 TMPM363F10FG PI1IE PI0IE ...
Page 180
... Port J data register Port J function register 2 Port J pull-up control register Port J input control register T19 T19 T19 Register name PJDATA PJFR2 PJPUP PJIE Page 154 TMPM363F10FG T18 T17 T17 Base Address = 0x400C_0900 Address (Base+) 0x0000 0x000C 0x002C 0x0038 0 T17 ...
Page 181
... Type 31-8 − R Read as 0. 7-0 PJ7 to PJ0 R Port J data register PJ5 PJ4 PJ3 Function Page 155 TMPM363F10FG PJ2 PJ1 PJ0 ...
Page 182
... PJ6F2 PJ5F2 PJ4F2 Read PORT 1: KWUP3 0: PORT 1: KWUP2 0: PORT 1: KWUP1 0: PORT 1: KWUP0 0: PORT 1: ADTRG Read as 0. Page 156 TMPM363F10FG PJ3F2 - - Function ...
Page 183
... PJ5UP PJ4UP PJ3UP Function PJ5IE PJ4IE PJ3IE Function Page 157 TMPM363F10FG PJ2UP PJ1UP PJ0UP ...
Page 184
... Port L pull-up control register Port L input control register T24 T23 T22 Register name PLDATA PLCR PLFR1 PLFR2 PLFR3 PLOD PLPUP PLIE Page 158 TMPM363F10FG T21 T20 T20 Base Address = 0x400C_0B00 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 0 ...
Page 185
... PL5 PL4 PL3 Function PL5C PL4C PL3C Function Page 159 TMPM363F10FG PL2 PL1 PL0 ...
Page 186
... PL6F1 PL5F1 PL4F1 Read PORT 1:INT1 0: PORT 1: SCLK1 0: PORT 1: RXD1 0: PORT 1: TXD1 0: PORT 1: INT0 0: PORT 1: SCK0 0: PORT 1: SCL0 / SI0 0: PORT 1: SDA0 / SO0 Page 160 TMPM363F10FG PL3F1 ...
Page 187
... PL2F2 R/W 0: PORT 1: TB2OUT 1 PL1F2 R/W 0: PORT 1: TB1OUT 0 PL0F2 R/W 0: PORT 1: TB0OUT PL5F2 PL4F2 PL3F2 Function Page 161 TMPM363F10FG PL2F2 PL1F2 PL0F2 ...
Page 188
... SCL3 0 : PORT 1 : SDA3 Read PL6OD PL5OD PL4OD Read CMOS 1 : Open-drain Page 162 TMPM363F10FG Function ...
Page 189
... PL5UP PL4UP PL3UP Function PL5IE PL4IE PL3IE Function Page 163 TMPM363F10FG PL2UP PL1UP PL0UP ...
Page 190
... Port M pull-up control register Port M input control register T29 T28 T27 Register name PMDATA PMCR PMFR1 PMFR2 PMFR3 PMOD PMPUP PMIE Page 164 TMPM363F10FG T21 T23 T26 Base Address = 0x400C_0C00 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 0 ...
Page 191
... PM5 PM4 PM3 Function PM5C PM4C PM3C Function Page 165 TMPM363F10FG PM2 PM1 PM0 ...
Page 192
... PM6F1 PM5F1 PM4F1 Read PORT 1: INT3 0: PORT 1: RXD3 0: PORT 1: TXD3 0: PORT 1: SCLK3 0: PORT 1: INT2 0: PORT 1: RXD2 0: PORT 1: TXD2 0: PORT 1: SCLK2 Page 166 TMPM363F10FG PM3F1 PM2F1 ...
Page 193
... PORT 1: TB3OUT 2 PM2F2 R/W 0: PORT 1: ALARM 1 PM1F2 R/W 0: PORT 1: TB1IN1 0 PM0F2 R/W 0: PORT 1: TB1IN0 PM3F2 PM2F2 Function Page 167 TMPM363F10FG PM1F2 PM0F2 ...
Page 194
... CTS3 Read PORT 1 : CTS2 PM6OD PM5OD PM4OD Read CMOS 1 : Open-drain Page 168 TMPM363F10FG Function ...
Page 195
... PM5UP PM4UP PM3UP Function PM5IE PM4IE PM3IE Function Page 169 TMPM363F10FG PM2UP PM1UP PM0UP ...
Page 196
... Port N pull-up control register Port N input control register − − − T30 Register name PNDATA PNCR PNFR1 PNFR2 PNFR3 PNOD PNPUP PNIE Page 170 TMPM363F10FG T25 T29 T28 Base Address = 0x400C_0D00 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 0 ...
Page 197
... PN3 PN2 Function PN3C PN2C Function Page 171 TMPM363F10FG PN1 PN0 ...
Page 198
... PN3F1 Read as 0. Write "0". 0: PORT 1: INT4 0: PORT 1: SCLK4 0: PORT 1: RXD4 0: PORT 1: TXD4 Page 172 TMPM363F10FG PN2F1 PN1F1 Function ...
Page 199
... Write "0". 5-4 − R Read PN3F2 R/W 0: PORT 1: TB2IN1 2 PN2F2 R/W 0: PORT 1: TB2IN0 1-0 − R Read PN3F2 PN2F2 Function Page 173 TMPM363F10FG ...
Page 200
... PN3F3 Read as 0. Write "0". Read PORT 1 : RMC 0 : PORT 1 : CTS4 Read as 0. Page 174 TMPM363F10FG PN2F3 - Function ...