TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 492

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

15.4
Operations
(7)
(8)
(9)
0 ms
Permissible value of signal transition timing on specification (Start bit)
CECRCR1 <CECRIHLD>, is valid.
dress does not correspond with the address set in the CECADD register.
error. An ACK response is , however, not performed, neither the header block nor the data block.
start bit detection respectively.
est start bit rising timing (the period that 1. indicates in the figure shown below).
imum cycle of a start bit (the period that 2. indicates in the figure shown below).
bit is considered to be valid.
Note 1: A broadcast message is received regardless of the <CECOTH> register setting.
Note 2: If the initiator sends a new message beginning with the start bit without having sent the last
Configure the CECRCR1<CECTOUT> bit to specify the time to determine a timeout.
This is used when the setting of a receive error interrupt suspension, which is specified in
By setting CECRCR1 <CECOTH>, you can specify if data is received or not when destination ad-
In this case, an ordinary data reception is performed and an interrupt is generated by detecting an
Configuring the CECRCR2 register allows you to specify the rising timing and a cycle of the
<CECSWAV0> is to specify the fastest start bit rising timing. <CECSWAV1> is to specify the lat-
<CECSWAV2> is to specify the minimum cycle of a start bit. <CECSWAV3> is to specify the max-
If a rising edge during the period 1. and a falling edge during the period 2. are detected, the start
Cycles to Identify Timeout
Data Reception at Logical Address Discrepancy
Start Bit Detection
block with EOM="1", a maximum cycle error is determined for the ACK bit and an interrupt is gen-
erated. Then, the receive operation is performed in the usual way.
<CECSWAV0>
115/fs ~ 115/fs - 7/fs
(approx.3.510ms)
3.5 ms
<CECSWAV1>
128/fs ~ 128/fs + 7/fs
(approx.3.906ms)
Page 466
1.
3.7 ms
<CECSWAV2>
141/fs - 7/fs ~ 141/fs
(approx.4.303ms)
4.3 ms
2.
<CECSWAV3>
154/fs ~ 154/fs + 7/fs
(approx.4.700ms)
4.7 ms
TMPM363F10FG