TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 493
TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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detection period
(10)
Error
CECRCR3 register.
specify the detection time in the <CECWAV0>, <CECWAV1>, <CECWAV2> and <CECWAV3>
bits.
ing described in 3., a waveform error interrupt is generated.
To detect an error when a received waveform is out of the defined tolerance range, configure the
An error is detected when the <CECWAVEN> bit of the CECRCR3 register is enabled. You can
If the rising edge is detected during the period 1. or 2. shown below, or not detected in the tim-
1. A period between the beginning of a bit and the fastest logical "1" rising timing
2. A period between the latest logical "1" rising timing and the fastest logical "0" rising timing.
3. The latest logical "0" rising timing.
Waveform Error Detection
Permissible value of signal transition timing on specification (Data bit)
0 ms
1.
<CECWAV0>
13/fs - 7/fs to 13/fs
(approx.0.396ms)
0.4 ms
<Logical ”1”>
<CECWAV1>
26/fs to 26/fs + 7/fs
(approx.0.793ms)
0.8 ms
Page 467
2.
<CECWAV2>
43/fs - 7/fs to 43/fs
(approx.1.312ms)
1.3 ms
<Logical ”0”>
<CECWAV3>
56/fs to 56/fs + 7/fs
(approx.1.709ms)
1.7 ms
3.
TMPM363F10FG
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