TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 49
TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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4. Memory Map
4.1
SRAM region and the special function register (SFR) is mapped to the peripheral region respectively.
SRAM and SFR regions are all included in the bit-band region.
fault if memory faults are disabled. Do not access the vendor-specific region.
Memory Map
The memory maps for the TMPM363F10FG are based on the ARM Cortex-M3 processor core memory map.
The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped to the
The special function register (SFR) indicates I/O ports and control registers for the peripheral function. The
The CPU register region is the processor core’s internal register region.
For more information on the each region, see the "Cortex-M3 Technical Reference Manual".
Note that access to regions indicated as "Fault" causes a memory fault if memory faults are enabled or a hard
Page 23
TMPM363F10FG
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