TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 433
TMPM363F10FG
Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM363F10FG.pdf
(788 pages)
Specifications of TMPM363F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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Note 1: Clear <BC[2:0]> to "000" before switching the operation mode to the SIO mode.
Note 2: For details on the SCL line clock frequency, refer to "14.5.1 Serial Clock".
Note 3: After a reset, the <SCK[0]/SWRMON> bit is read as "1". However, if the SIO mode is selected at the
Note 4: The initial value for selecting a frequency is <SCK[2:0]>=000 and is independent of the read initial value.
Note 5: When <BC[2:0]>="001" and <ACK>="0" in master mode, SCL line may be fixed to "L" by falling edge of
SBIxCR2 register, the initial value of the <SCK[0]> bit is "0".
SCL line after generation of STOP condition and other master devices can not use the bus. In the case
of bus which is connected with several master devices, the number of bits per transfer should be set
equal or more than 2 before generation of STOP condition.
Page 407
TMPM363F10FG
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