TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 485

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TMPM363F10FG

Manufacturer Part Number
TMPM363F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM363F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14x14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
4
Uart/sio (ch)
5
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
8
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM363F10FG
Manufacturer:
Toshiba
Quantity:
10 000
15.3.13
31-7
6
5
4
3
2
1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
CECRIWAV
CECRIOR
CECRIACK
CECRIMIN
CECRIMAX
CECRISTA
CECRIEND
Bit Symbol
Note:Writing to this bit is ignored.
CECRSTAT (Receive Interrupt Status Register)
31
23
15
0
0
0
7
0
-
-
-
-
R
R
R
R
R
R
R
R
Type
CECRIWAV
30
22
14
0
0
0
6
0
Read as 0.
Interrupt flag
0: No wave form error
1: Wave form error
Indicates that waveform error is detected.
The error occurs when waveform error detection is enabled in CECRCR3 <CECWAVEN>.
Interrupt flag
0: No receive buffer overrun
1:Receive buffer overrun
Indicates the receive buffer receives next data before reading the data that had already been set.
Interrupt flag
0: No ACK collision
1: ACK collision
Indicates "0" is detected after the specified time to output ACK bit "0".
Interrupt flag
0: No minimum cycle error
1:Minimum cycle error
Indicates one bit cycle is shorter than the minimum cycle error detection time specified in
CECRCR1<CECMIN>.
Interrupt flag
0: No maximum cycle error
1: Maximum cycle error
Indicates one bit cycle is longer than the maximum cycle error detection time specified in
CECRCR1<CECMAX>.
Interrupt flag
0: No start bit detection
1: Start bit detection
Indicates a start bit is detected.
Interrupt flag
0: Not one byte data reception completed
1: Completion of 1 byte data reception
Indicates 1 byte of data reception is completed.
-
-
-
CECRIOR
29
21
13
0
0
0
5
0
-
-
-
CECRIACK
Page 459
28
20
12
0
0
0
4
0
-
-
-
CECRIMIN
27
19
11
Function
0
0
0
3
0
-
-
-
CECRIMAX
26
18
10
0
0
0
2
0
-
-
-
CECRISTA
25
17
0
0
9
0
1
0
-
-
-
TMPM363F10FG
CECRIEND
24
16
0
0
8
0
0
0
-
-
-

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