TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 368

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

12.7
Clock Control
12.7.2
12.7.2.1
12.7.2.2
cuits in which clocks can be selected by the settings of the baud rates generator and modes.
The serial clock circuit is a block to generate transmit and receive clocks (SIOCLK) and consists of the cir-
rate.
Serial Clock Generation Circuit
(1)
(2)
(1)
The baud rate generator generates transmit and receive clocks to determine the serial channel transfer
A clock can be selected by setting the modes and the register.
Modes can be specified by setting the SCxMOD0<SM>.
The input clock in I/O interface mode is selected by setting SCxCR.
The clock in UART mode is selected by setting SCxMOD0<SC>.
Baud Rate Generator
Clock Selection Circuit
32 and 128.
and SCxBRADD.
mode, either 1/N or N + (16-K)/16 in the UART mode.
The input clock of the baud rate generator is selected from the prescaler outputs divided by 2, 8,
This input clock is selected by setting the SCxBRCR<BRCK>.
The frequency division ratio of the output clock in the baud rate generator is set by SCxBRCR
The following frequency divide ratios can be used; 1/N frequency division in the I/O interface
The table below shows the frequency division ratio which can be selected.
Table 12-7 shows clock selection in I/O interface mode.
Note:1/N (N=1)frequency division ratio can be used only when a double buffer is enabled.
Buad Rate Generator input clock
Baud Rate Generator output clock
Transfer Clock in I/O interface mode
I/O interface
UART
Mode
Divide Function Setting
SCxBRCR<BRADDE>
N + (16-K)/16 division
Divide by N
Divide by N
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SCxBRCR<BRS>
1 to 16 (Note)
Divide by N
1 to 16
2 to 15
SCxBRADD<BRK>
Divide by K
1 to 15
TMPM363F10FG
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