TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 92

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

7.2
Reset Exceptions
7.2
7.3
7.4
Note:
trol and Status Register, the counter loads with the value set in the Reload Value Register and begins counting
down.When the counter reaches "0", a SysTick exception occurs.You may be pending exceptions and use a flag
to know when the timer reaches "0".
count clock frequency varies with each product, and so the value set in the SysTick Calibration Value Register al-
so varies with each product.
Reset Exceptions
SysTick
Reset exceptions are generated from the following three sources.
Use the Reset Flag (CGRSTFLG) Register of the Clock Generator to identify the source of a reset.
Non-Maskable Interrupts (NMI)
Non-maskable interrupts are generated from the following two sources.
Use the NMI Flag (CGNMIFLG) Register of the clock generator to identify the source of a non-maskable interrupt.
SysTick provides interrupt features using the CPU's system timer.
When you set a value in the SysTick Reload Value Register and enable the SysTick features in the SysTick Con-
The SysTick Calibration Value Register holds a reload value for counting 10 ms with the system timer. The
Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from
・ External reset pin
・ Reset exception by WDT
・ Reset exception by SYSRESETREQ
・ External NMI pin
・ Non-maskable interrupt by WDT
Do not reset with <SYSRESETREQ> in SLOW mode.
the X1 pin by 32.The SysTick Calibration Value Register is set to 0x9C4, which provides 10 ms tim-
ing when the clock input from X1 is 8 MHz.
set Control Register.
ter on the WDT.
A reset exception occurs when an external reset pin changes from "Low" to "High".
The watchdog timer (WDT) has a reset generating feature. For details, see the chapter on the WDT.
A reset can be generated by setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Re-
A non-maskable interrupt is generated when an external NMI pin changes from "High" to "Low".
The watchdog timer (WDT) has a non-maskable interrupt generating feature. For details, see the chap-
Page 66
TMPM363F10FG