TMPM363F10FG Toshiba, TMPM363F10FG Datasheet - Page 591

• Manufacturer Part Number: TMPM363F10FG
• Manufacturer: Toshiba

Specifications of TMPM363F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 100
• Package: LQFP(14x14)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 4
• Uart/sio (ch): 5
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: 8
• 10-bit Ad Converter: 8
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

18.6.5
31
30
29-7
6
5
4
3
2
1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
Status register. The HcInterruptEnable register is used to control which events generate a hardware interrupt.
When a bit is set in the HcInterruptStatus register and the corresponding bit in the HcInterruptEnable register
is set and the MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus.
ter leaves the corresponding bit unchanged. On read, the current value of this register is returned.
MIE
OC
−
RHSC
FNO
UE
RD
SF
WDH
SO
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterrupt-
Writing a "1" to a bit in this register sets the corresponding bit, whereas writing a "0" to a bit in this regis-
Bit Symbol
HcInterruptEnable Register
MIE
31
23
15
0
7
-
-
-
R/W
R/W
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(HCD)
Type
RHSC
OC
30
22
14
0
6
0
R
R
−
R
R
R
R
R
R
R
-
-
Type
(HC)
Filed name:Master Interrupt Enable
A '0' written to this field is ignored by HC. A '1' written to this field enables interrupt generation
due to events specified in the other bits of this register. This is used by HCD as a Master Inter-
rupt Enable.
Filed name:Ownership Change
0: Ignore
1: Enable interrupt generation due to Ownership Change.
Reserved
Filed name:Root Hub Status Change
0: Ignore
1:Enable interrupt generation due to Root Hub Status Change.
Filed name:Frame Number Overflow
0: Ignore
1: Enable interrupt generation due to Frame Number Overflow.
Filed name:Unrecoverable Error
0: Ignore
1: Enable interrupt generation due to Unrecoverable Error.
Filed name:Resume Detected
0: Ignore
1: Enable interrupt generation due to Resume Detected.
Filed name:Startof Frame
0: Ignore
1: Enable interrupt generation due to Start of Frame.
Filed name:Writeback Done Head
0: Ignore
1: Enable interrupt generation due to HcDoneHeadWriteback.
Filed name:Scheduling Overrun
0: Ignore
1: Enable interrupt generation due to Scheduling Overrun.
FNO
29
21
13
5
0
-
-
-
Page 565
UE
28
20
12
4
0
-
-
-
RD
27
19
11
3
0
-
-
-
Function
SF
26
18
10
2
0
-
-
-
WDH
25
17
9
1
0
-
-
-
TMPM363F10FG
SO
24
16
8
0
0
-
-
-