MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet
MSC8101DS
Related parts for MSC8101DS
MSC8101DS Summary of contents
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MOTOROLA Semiconductor Products Sector Technical Data Advance Information Networking Digital Signal Processor The Motorola MSC8101 16-bit Digital Signal Processor (DSP) is the first member of the family of DSPs based on the Star*Core™ SC140 DSP core. This very versatile chip ...
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Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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FEATURES SC140 Core Architecture optimized for efficient C/C++ code compilation Four 16-bit ALUs and two 32-bit AGUs 1200 DSP MIPS, 3000 RISC MIPS, running at 300 MHz Very low power dissipation—less than 0.25W for the core running full speed at ...
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DMA controller 16 DMA channels, FIFO based, with burst capabilities Sophisticated addressing capabilities Small foot print package plastic package Very low power consumption Estimated power consumption of 500 mW for the entire device Separate power supply ...
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PRODUCT DOCUMENTATION The three documents listed in the following table, once they are available, will be required for a complete description of the MSC8101 and will be necessary to design properly with the part. Documentation will be available from the ...
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MSC8101 Technical Data ...
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Chapter 1 Signal/Connection Descriptions The MSC8101 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1-1 lists the functional groups, the number of signal connections in each group, and references the ...
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VCCSYN1 GNDSYN1 For the signals PB[31–18] multiplexed on Ports A–D, see Figure 1-2 PC[31–22, 15–12, 7–4] PD[31–29, 19–16, 7] EOnCE Event Configuration EED EE0 EE1 EE[2–3] EE[4–5] BTM[0–1] PORESET RSTCONF BNKSEL[0–2] TC[0–2] MODCK[1–3] THERM[1–2] SPARE1, SPARE5 Refer to the System ...
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FCC1 ATM/UTOPIA FCC1 MPHY MPHY Master HDLC/ Master HDLC Ethernet mux poll transp. dir. poll MII or Slave Serial Nibble TXENB COL TXCLAV TXCLAV0 CRS RTS TXSOC TX_ER RXENB TX_EN RXSOC RX_DV RXCLAV RXCLAV0 RX_ER TXD0 TXD1 TXD2 TXD3 TXD4 ...
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Power Signals Table 1-2. Power and Ground Signal Inputs Power Name V Internal Logic Power DD V dedicated for use with the device core. The voltage should be well-regulated and the input DD should be provided with an extremely ...
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Clock Signals Signal Type Name CLKIN Input Clock In Primary clock input to the MSC8101 PLL. MODCK1 Input Clock Mode Input 1 Defines the operating mode of internal clock circuits. TC0 Output Transfer Code 0 Supplies information that can ...
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Reset, Configuration, and EOnCE Event Signals Table 1-4. Reset, Configuration, and EOnCE Event Signals Signal Name Type DBREQ Input Debug Request Determines whether to go into SC140 Debug mode when PORESET is deasserted. 1 EE0 Enhanced OnCE (EOnCE) Event ...
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Table 1-4. Reset, Configuration, and EOnCE Event Signals (Continued) Signal Name Type BTM[0–1] Input Boot Mode 0–1 Determines the MSC8101 boot mode when PORESET is deasserted. See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for ...
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PowerPC System Bus, HDI16, and Interrupt Signals The PowerPC System Bus, HDI16, and Interrupt signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured ...
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Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Reserved Output The primary configuration is reserved. BADDR29 Output Burst Address 29 One of five outputs of the memory controller. These pins connect directly to memory devices ...
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Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow TS Input/Output Bus Transfer Start Signals the beginning of a new address bus tenure. The MSC8101 asserts this signal when one of its internal bus masters (SC140 ...
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Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow D52 Input/Output Data Bus Bit 52 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid ...
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Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow D56 Input/Output Data Bus Bit 56 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid ...
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Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Reserved Input The primary configuration is reserved. DP0 Input/Output Data Parity 0 The agent that drives the data bus also drives the data parity signals. The value ...
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Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow IRQ4 Input Interrupt Request 4 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP4 Input/Output ...
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Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow TA Input/Output Transfer Acknowledge Indicates that a data beat is valid on the data bus. For single beat transfers, assertion of TA indicates the termination of the ...
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Memory Controller Signals Refer to the Memory Controller chapter in the MSC8101 Technical Reference Manual for detailed information about configuring these signals. Signal Data Flow CS[0–7] Output Chip Select Enable specific memory devices or peripherals connected to MSC8101 buses. ...
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Table 1-6. Memory Controller Signals (Continued) Signal Data Flow POE Output Bus Output Enable Output of the bus GPCM. Controls the output buffer of memory devices during read operations. PSDRAS Output Bus SDRAM RAS Output from the bus SDRAM controller. ...
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Communications Processor Module (CPM) Ports The MSC8101 Communications Processor Module (CPM) supports a subset of signals included in the MPC8260. The following sections describe the functionality of the signals in the MSC8101. The MSC8101 CPM includes the following set ...
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Time-Slot Assigner (TSA) that supports multiplexing from any of the SCCs, FCCs, SMCs, and two MCCs onto four time-division multiplexed (TDM) interfaces. The TSA uses two Serial Interfaces (SI1 and SI2). SI1 uses TDMA1 which supports both serial and nibble ...
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Port A Signals Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA30 FCC1: TXCLAV UTOPIA slave FCC1: TXCLAV UTOPIA master , or FCC1: TXCLAV0 UTOPIA master, Multi-PHY, direct polling FCC1: RTS HDLC, Serial and Nibble FCC1: CRS MII PA29 ...
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Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA28 FCC1: RXENB UTOPIA master FCC1: RXENB UTOPIA slave FCC1: TX_EN MII PA27 FCC1: RXSOC UTOPIA master FCC1: RXSOC UTOPIA slave FCC1: RX_DV MII Table 1-7. Port A Signals (Continued) Dedicated ...
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Port A Signals Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA26 FCC1: RXCLAV UTOPIA slave FCC1: RXCLAV UTOPIA master, or RXCLAV0 UTOPIA master, Multi-PHY, direct polling FCC1: RX_ER MII PA25 FCC1: TXD0 UTOPIA SDMA: MSNUM0 PA24 FCC1: TXD1 ...
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Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA22 FCC1: TXD3 UTOPIA PA21 FCC1: TXD4 UTOPIA FCC1: TXD3 MII and HDLC nibble PA20 FCC1: TXD5 UTOPIA FCC1: TXD2 MII and HDLC nibble PA19 FCC1: TXD6 UTOPIA FCC1: TXD1 MII ...
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Port A Signals Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA18 FCC1: TXD7 UTOPIA FCC1: TXD0 MII and HDLC nibble FCC1: TXD HDLC serial and transparent PA17 FCC1: RXD7 UTOPIA FCC1: RXD0 MII and HDLC nibble FCC1: RXD ...
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Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA15 FCC1: RXD5 UTOPIA RXD2 MII and HDLC nibble PA14 FCC1: RXD4 UTOPIA FCC1: RXD3 MII and HDLC nibble PA13 FCC1: RXD3 UTOPIA SDMA: MSNUM2 Table 1-7. Port A Signals (Continued) ...
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Port A Signals Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA12 FCC1: RXD2 UTOPIA SDMA: MSNUM3 PA11 FCC1: RXD1 UTOPIA SDMA: MSNUM4 PA10 FCC1: RXD0 UTOPIA SDMA: MSNUM5 PA9 SMC2: SMTXD SI1 TDMA1: L1TXD0 TDM nibble 1-26 Table ...
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Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA8 SMC2: SMRXD SI1 TDMA1: L1RXD0 TDM nibble SI1 TDMA1: L1RXD TDM serial PA7 SMC2: SMSYN SI1 TDMA1: L1TSYNC/GRANT TDM nibble and TDM serial PA6 SI1 TDMA1: L1RSYNC TDM nibble and ...
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Port B Signals 1.6.2 Port B Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PB31 FCC2: TX_ER MII SCC2: RXD SI2 TDMB2: L1TXD TDM serial PB30 SCC2: TXD FCC2: RX_DV MII SI2 TDMB2: L1RXD TDM serial PB29 FCC2: ...
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Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PB28 FCC2: RTS HDLC serial , HDLC nibble , and transparent FCC2: RX_ER MII SCC2: RTS, TENA SI2 TDMB2: L1TSYNC/GRANT TDM serial PB27 FCC2: COL MII SI2 TDMC2: L1TXD TDM serial ...
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Port B Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PB25 FCC2: TXD3 MII and HDLC nibble SI1 TDMA1: L1TXD3 TDM nibble SI2 TDMC2: L1TSYNC/GRANT TDM serial PB24 FCC2: TXD2 MII and HDLC nibble SI1 TDMA1: L1RXD3 nibble ...
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Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PB22 FCC2: TXD0 MII and HDLC nibble FCC2: TXD HDLC serial and transparent SI1 TDMA1: L1RXD1 TDM nibble SI2 TDMD2: L1RXD TDM serial PB21 FCC2: RXD0 MII and HDLC nibble FCC2: ...
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Port B Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PB20 FCC2: RXD1 MII and HDLC nibble SI1 TDMA1: L1TXD1 TDM nibble SI2 TDMD2: L1RSYNC TDM serial PB19 FCC2: RXD2 MII and HDLC nibble SDA ...
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Port C Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC31 BRG1O CLK1 TIMER1/2: TGATE1 PC30 BRG2O CLK2 Timer1: TOUT1 EXT1 Table 1-9. Port C Signals Dedicate d I/O Data Direction Output Baud-Rate Generator 1 Output The ...
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Port C Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC29 BRG3O CLK3 TIN2 SCC1: CTS, CLSN PC28 BRG4O CLK4 TIN1 Timer2: TOUT2 SCC2: CTS, CLSN 1-34 Table 1-9. Port C Signals (Continued) Dedicate d I/O Data Direction ...
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Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC27 BRG5O CLK5 TIMER3/4: TGATE2 PC26 BRG6O CLK6 Timer3: TOUT3 TMCLK Table 1-9. Port C Signals (Continued) Dedicate d I/O Data Direction Output Baud-Rate Generator 5 Output The CPM supports up ...
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Port C Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC25 BRG7O CLK7 TIN4 DMA: DACK2 PC24 BRG8O CLK8 TIN3 Timer4: TOUT4 DMA: DREQ2 1-36 Table 1-9. Port C Signals (Continued) Dedicate d I/O Data Direction Output Baud-Rate ...
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Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC23 CLK9 DMA: DACK1 EXT2 PC22 SI1: L1ST1 CLK10 DMA: DREQ1 Table 1-9. Port C Signals (Continued) Dedicate d I/O Data Direction Input Clock 9 The CPM supports ...
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Port C Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC15 SMC2: SMTXD SCC1: CTS/CLSN FCC1: TXADDR0 UTOPIA master FCC1: TXADDR0 UTOPIA slave PC14 SI1: L1ST2 SCC1: CD, RENA FCC1: RXADDR0 UTOPIA master FCC1: RXADDR0 UTOPIA slave 1-38 ...
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Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC13 SI1: L1ST4 SCC2: CTS,CLSN FCC1:TXADDR1 UTOPIA master FCC1: TXADDR1 UTOPIA slave PC12 SI1: L1ST3 SCC2: CD, RENA FCC1: RXADDR1 UTOPIA master FCC1: RXADDR1 UTOPIA slave Table 1-9. Port C Signals ...
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Port C Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC7 SI2: L1ST1 FCC1: CTS HDLC serial , HDLC nibble , and transparent FCC1: TXADDR2 UTOPIA master FCC1: TXADDR2 UTOPIA slave FCC1: TXCLAV1 UTOPIA multi-PHY master, direct polling ...
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Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC6 SI2: L1ST2 FCC1: CD HDLC serial , HDLC nibble , and transparent FCC1: RXADDR2 UTOPIA master FCC1: RXADDR2 UTOPIA slave FCC1: RXCLAV1 UTOPIA multi-PHY master, direct polling PC5 SMC1: SMTXD ...
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Port C Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC4 SMC1: SMRXD SI2: L1ST4 FCC2: CD HDLC serial , HDLC nibble , and transparent 1-42 Table 1-9. Port C Signals (Continued) Dedicate d I/O Data Direction Input ...
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Port D Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PD31 SCC1: RXD DMA: DRACK1 DMA: DONE1 PD30 SCC1: TXD DMA: DRACK2 DMA: DONE2 Table 1-10. Port D Signals Dedicate d I/O Data Direction Input SCC1: Receive ...
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Port D Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PD29 SCC1: RTS, TENA FCC1: RXADDR3 UTOPIA master FCC1: RXADDR3 UTOPIA slave FCC1: RXCLAV2 UTOPIA multi-PHY master, direct polling 1-44 Table 1-10. Port D Signals (Continued) Dedicate d ...
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Table 1-10. Port D Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PD19 FCC1: TXADDR4 UTOPIA master FCC1: TXADDR4 UTOPIA slave FCC1: TXCLAV3 UTOPIA multi-PHY master, direct polling BRG1O SPI: SPISEL Dedicate d I/O Data Direction Output ...
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Port D Signals Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PD18 FCC1: RXADDR4 UTOPIA master FCC1: RXADDR4 UTOPIA slave FCC1: RXCLAV3 UTOPIA multi-PHY master, direct polling SPI: SPICLK PD17 BRG2O FCC1: RXPRTY UTOPIA SPI: SPIMOSI 1-46 Table 1-10. ...
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Table 1-10. Port D Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PD16 FCC1: TXPRTY UTOPIA SPI: SPIMISO PD7 SMC1: SMSYN FCC1: TXADDR3 UTOPIA master FCC1: TXADDR3 UTOPIA slave FCC1: TXCLAV2 UTOPIA multi-PHY master, direct polling Dedicate ...
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Port D Signals 1.7 JTAG Test Access Port Signals The MSC8101 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-11. Table 1-11. ...
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Chapter 2 Hardware Specifications 2.1 Introduction This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MSC8101 communications processor. For additional information, see the MSC8101 User’s Manual. Note: The MSC8101 electrical specifications are ...
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Table 2-1 describes the maximum electrical ratings for the MSC8101. Rating Core supply voltage PLL supply voltage I/O supply voltage Input voltage Maximum operating temperature range Storage temperature range Note: 1. Functional operating conditions are given in Table 2-2. 2. ...
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Thermal Characteristics Table 2-3 describes thermal characteristics of the MSC8101. Characteristic 1, 2 Junction-to-ambient Junction-to-ambient, four-layer board 4 Junction-to-board (bottom) 5 Junction-to-case (top) 6 Junction-to-package (top) Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal ...
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DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8101. The measurements in Table 2-4 assume the following system conditions 0–70 ° 1.5 V ± ...
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AC Timings The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. AC timings are based load, except where noted otherwise, and 50 2.5.1 Clock and Timing Signals ...
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Clock and Timing Signals Table 2-6. Clock Configuration Modes 1 Mode # MODCK_H MODCK[1–3] 0 000 000 1 000 001 2 000 010 3 000 011 4 000 100 5 000 101 6 000 110 7 000 111 8 001 ...
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Table 2-6. Clock Configuration Modes (Continued) 1 Mode # MODCK_H MODCK[1–3] 35 100 011 36 100 100 37 100 101 38 100 110 39 100 111 40 101 000 41 101 001 42 101 010 43 101 011 44 101 ...
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Clock and Timing Signals Key: SPLL PDF: System PLL Pre-Division Factor SPLL MF: System PLL Multiplication Factor DLL: Delay Lock Loop Bus DF: Bus Division Factor SCC DF: SCC Division Factor CPM DF: CPM Division Factor BRG DF: Baud Rate ...
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Clocking and Timing Characteristics Characteristic Phase Jitter between BCLK and DLLIN 1 CLKIN frequency CLKIN slope DLLIN slope CLKOUT frequency jitter Delay between CLKOUT and DLLIN Note: 1. Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency ...
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Reset Timing 2.5.2 Reset Timing The MSC8101 has several inputs to the reset logic: Power-on reset (PORESET) External hard reset (HRESET) External soft reset (SRESET) Asserting an external PORESET causes concurrent assertion of an internal PORESET signal, HRESET, and SRESET. ...
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Table 2-10. External Configuration Signals Pin Description RSTCONF Reset Configuration Input line sampled by the MSC8101 at the rising edge of PORESET. DBREQ/ EONCE Event Bit 0 EE0 Input line sampled after SC140 core PLL locks. Holding EE0 high when ...
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Reset Timing No. Characteristics 6 Delay from SPLL lock to SRESET deassertion DLL enabled — BCLK = 20 MHz — BCLK = 100 MHz DLL disabled — BCLK = 20 MHz — BCLK = 100 MHz Notes: 1. Value given ...
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RSTCONF, HPE PORESET asserted for Input HRM, BTM min 16 pins are sampled CLKIN. PORESET Internal Any time Reset Configuration HRESET Output (I/O) SRESET Output (I/O) Figure 2-2. Host Reset Configuration Timing Directly after the deassertion of PORESET configuration ...
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Reset Timing 1 PORESET Input asserted for RSTCONF is sampled for min 16 master/slave determination CLKIN. PORESET Internal HRESET Output (I/O) SRESET Output (I/O) In reset configuration mode: reset configuration sequence occurs in this period. Figure 2-3. Hardware Reset Configuration ...
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PowerPC System Bus Access Timing 2.5.3.1 Core Data Transfers Generally, all MSC8101 bus and system output signals are driven from the rising edge of the input clock (CLKIN). Memory controller signals, however, trigger on four points within a CLKIN ...
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PowerPC System Bus Access Timing Table 2-14. AC Characteristics for SIU Outputs Number 31 PSDVAL/TEA/TA delay from CLKIN rising edge 32a Address bus/Address attributes/GBL delay from CLKIN rising edge 32b BADDR delay from CLKIN rising edge 33a Data bus delay ...
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DMA Data Transfers Table 2-15 describes the DMA signals. Number 36 DREQ setup time before CLKIN falling edge 37 DREQ hold time after CLKIN falling edge 38 DONE setup time before CLKIN rising edge 39 DONE hold time after ...
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HDI16 Signals 2.5.4 HDI16 Signals Table 2-16. Host Interface (HDI16) Timing Number Characteristics 42 Read data strobe assertion width HACK read assertion width 43 Read data strobe deassertion width HACK read deassertion width 44 Read data strobe deassertion width 5,6 ...
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Table 2-16. Host Interface (HDI16) Timing Number Characteristics 55 HCS[1–2] assertion to output data valid 56 HCS[1–2] hold time after data strobe deassertion 57 HA[0–3], HRW setup time before data strobe 9 assertion Read Write 58 HA[0–3], HRW hold time ...
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HDI16 Signals Figure 2-7 shows HDI16 Read signals timing. HA[0–3] HRW HCS[1–2] HRD, HDS HD[0–15] HREQ, HRRQ, HTRQ 2- Figure 2-7. Read Timing Diagram MSC8101 Technical Data ...
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Figure 2-8 shows HDI16 write signals timing. HA[0–3] HRW HCS[1–2] HWR, HDS HD[0–15] HREQ, HRRQ, HTRQ Figure 2-9 shows Host DMA write timing. (Output) HACK or HWR,HDS, HD[0–15] Figure 2-9. Host DMA Write Timing Diagram ...
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CPM Timings Figure 2-10 shows Host DMA read timing. HWR,HDS, HD[0–15] Figure 2-10. Host DMA Read Timing Diagram 2.5.5 CPM Timings No. 16 FCC input setup time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock ...
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No. 36 FCC output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock SCC/SMC/SPI/I C output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock) 40 ...
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CPM Timings SCC/SMC/SPI/I SCC/SMCSPI/I Figure 2-14. SCC/SMC/SPI/I Serial input clock TDM inputs TDM outputs PIO/TIMER/DMA inputs PIO/TIMER/DMA outputs Figure 2-16. PIO, Timer, and DMA Signal Diagram Note: The timing values listed are preliminary and refer to minimum system timing requirements. ...
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EE Signals Number Characteristics 65 EE pins as inputs 66 EE pins as outputs Note: 1. GCLK is the DSP core clock. The ratio between the DSP clock and CLKOUT is configured during power-on-reset. See Table 2-6 on page ...
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JTAG Signals 2.5.7 JTAG Signals No. Characteristics 500 TCK frequency of operation 501 TCK cycle time 502 TCK clock pulse width measured at 1.5 V 503 TCK rise and fall times 504 Boundary scan input data set-up time 505 Boundary ...
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TCK V (Input) IL TDI TMS (Input) 510 TDO (Output) 511 TDO (Output) 510 TDO (Output) Figure 1-2. Test Access Port Timing Diagram TCK (Input) 513 TRST (Input) 512 Figure 1-3. TRST Timing Diagram 508 Input Data Valid Output Data ...
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JTAG Signals 2-28 MSC8101 Technical Data ...
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Chapter 3 Packaging 3.1 Pinout and Package Information This sections provides information about the MSC8101 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1, Signal/Connection Descriptions are allocated. The MSC8101 is available ...
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D4 D7 D11 D1 A IRQ5 D3 D6 D10 IRQ1 D0 IRQ3 B THERM IRQ4 DP0 1 THERM D8 D EE1 IRQ2 IRQ6 EE0 2 VDDH VDD VDDH EE4 EE2 ...
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A D62 D63 D55 D51 D60 BADDR B DBG PWE6 D54 D50 D59 28 BADDR C D61 DBB D53 D49 D58 29 D BADDR GBL PWE5 D48 D57 D52 27 MOD PSD E PSDA ...
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Table 3-1. MSC8101 Signal Listing By Name 3-4 Signal Name Number A0 W15 A1 N14 A2 V15 A3 T14 A4 U15 A5 W16 A6 V16 A7 W17 A8 U16 A9 V17 A10 W18 A11 U17 A12 T16 A13 V18 A14 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name A31 AACK ABB ALE ARTRY BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BR BTM0 BTM1 CLKIN CLKOUT CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 D0 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) 3-6 Signal Name Number D10 B6 D11 A6 D12 G7 D13 E7 D14 D7 D15 C7 D16 B7 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DBB ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) 3-8 Signal Name Number DLLIN P8 DP0 C2 DP1 B1 DP2 D4 DP3 B2 DP4 C3 DP5 A2 DP6 D5 DP7 F6 DACK3 D5 DACK4 F6 DREQ3 C3 DREQ4 A2 EE0 D2 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) 3-10 Signal Name Number GNDSYN V7 GNDSYN1 U7 H8BIT B16 HA0 D14 HA1 C14 HA2 B14 HA3 A14 HACK/HACK E16 HCS1/HCS1 D15 HCS2/HCS2 A16 HD0 A10 HD1 G11 HD2 D11 HD3 C11 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name HRESET HRRQ/HRRQ HRW HTRQ/HTRQ HWR/HWR INT_OUT IRQ1 IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ5 IRQ5 IRQ6 IRQ7 IRQ7 MODCK1 MODCK2 MODCK3 NMI NMI_OUT PA6 PA7 PA8 PA9 PA10 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) 3-12 Signal Name Number PA13 U8 PA14 W8 PA15 W3 PA16 M7 PA17 T4 PA18 W2 PA19 R5 PA20 T3 PA21 U1 PA22 R3 PA23 P4 PA24 P2 PA25 N2 PA26 M6 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name PB31 PBS0 PBS1 PBS2 PBS3 PBS4 PBS5 PBS6 PBS7 PC4 PC5 PC6 PC7 PC12 PC13 PC14 PC15 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PD7 PD16 PD17 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) 3-14 Signal Name Number PD29 K2 PD30 J2 PD31 H2 PGPL0 E17 PGPL1 F14 PGPL2 G19 PGPL3 E19 PGPL4 J18 PGPL5 J17 PGTA J18 POE G19 PORESET W5 PPBS J18 PSDA10 E17 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name PWE4 PWE5 PWE6 PWE7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved RSTCONF SPARE1 SPARE5 SRESET TA TBST TC0 TC1 TC2 TCK TDI TDO TEA TEST THERM1 THERM2 TMS TRST TS ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) 3-16 Signal Name Number TSZ2 W12 TSZ3 N11 TT0 N13 TT1 N12 TT2 U14 TT3 V14 TT4 W14 VCCSYN W7 VCCSYN1 T7 VDD E12 VDD E5 VDD E9 VDD F16 VDD F4 ...
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Table 3-1. MSC8101 Signal Listing By Name (Continued) Signal Name VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH Table 3-2. MSC8101 Signal Listing by Pin Designator Number Signal Name A2 IRQ5 / ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number A14 A15 A16 A17 A18 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number C9 C10 C11 C12 C13 C14 C15 D53 / HRW / HRD C16 C17 C18 C19 BADDR29 / IRQ2 D1 D2 DBREQ / EE0 D3 D4 IRQ2 / DP2 / ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 F10 F11 F12 F13 ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number F16 F17 PWE7 / PSDDQM7 / PBS7 F18 MODCK2 / TC1 / BNKSEL1 F19 G10 G11 G12 G13 G14 G15 G16 ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number H15 H16 H17 H18 H19 J13 J14 J15 J16 J17 J18 J19 K13 K14 K15 K16 ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number K19 L13 L14 L15 L16 L17 L18 L19 M13 M14 M15 M16 M17 M18 M19 N1 ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 P10 P11 P12 P13 P14 ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number P17 P18 P19 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number T11 T12 T13 T14 T15 T16 T17 T18 T19 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 V1 V2 ...
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Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued) Number V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W10 W11 IRQ7 / INT_OUT W12 W13 ...
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FC-PBGA Package Mechanical Drawing Figure 3-3. MSC8101 Mechanical Information, 332-pin FC-PBGA Package 3-28 CASE 1169-01 MSC8101 Technical Data Notes: 1. Dimensions and tolerancing per ASME Y14.5, 1994. 2. Dimensions in millimeters. 3. Dimension b is the maximum solder ball ...
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Chapter 4 Design Considerations 4.1 Thermal Design Considerations The average chip-junction temperature Equation where = ambient temperature package thermal resistance ...
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Power Considerations The internal power dissipation consists of three components INT CORE SIU CPM The power dissipation depends on the operating frequency of the different portions of the chip. The numbers given ...
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P (200) = ((P – P CORE CORE P (50) = ((P – 100) SIU SIU LSI P (100) = ((P – P CPM CPM (200 INT CORE SIU ...
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MSC8101 Technical Data ...
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...
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ORDERING INFORMATION Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Supply Part Voltage MSC8101 1.5 V core Flip Chip Plastic Ball Grid Array 3.3 V I/O OnCE, StarCore, DigitalDNA, and ...