MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 51

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

General-
Purpose
PD19
I/O
FCC1: TXADDR4
UTOPIA master
FCC1: TXADDR4
UTOPIA slave
FCC1: TXCLAV3
UTOPIA multi-PHY master,
direct polling
BRG1O
SPI: SPISEL
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-10. Port D Signals (Continued)
Direction
MSC8101 Technical Data
Dedicate
Output
Output
d I/O
Input
Input
Input
Data
FCC1: Multi-PHY Master Transmit Address Bit 4
Multiplexed Polling
In the ATM UTOPIA master interface supported by FCC1 using
multiplexed polling, this is transmit address bit 4.
FCC1: UTOPIA Slave Transmit Address Bit 4
In the ATM UTOPIA slave interface supported by FCC1 using
multiplexed polling, this is transmit address bit 4.
FCC1: UTOPIA Multi-PHY master Transmit Cell Available 3
Direct Polling
In the ATM UTOPIA master interface supported by FCC1 using
direct polling, TXCLAV3 is asserted by an external UTOPIA
slave PHY to indicate that it can accept one complete ATM cell.
Baud Rate Generator 1 Output
The CPM supports up to 8 BRGs. The BRGs can be used
internally by the bank-of-clocks selection logic and/or provide
an output to one of the 8 BRG pins. BRG1O can be the internal
input to the SIU timers. When CLK5 is selected (see PC27
above), it is the source for BRG1O which is the default input for
the SIU timers. See the System Interface Unit (SIU) chapter in
the MSC8101 Technical Reference manual for additional
information. If CLK5 is not enabled, BRG1O uses an internal
input. If TMCLK is enabled (see PC26 above), the BRG1O
input to the SIU timers is disabled.
SPI: Select
The SPI interface comprises four signals: master out slave in
(SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and
select (SPISEL). The SPI can be configured as a slave or
master in single- or multiple-master environments. SPISEL is
the enable input to the SPI slave. In a multimaster environment,
SPISEL (always an input) detects an error when more than one
master is operating. SPI masters must output a slave select
signal to enable SPI slave devices by using a separate
general-purpose I/O signal. Assertion of an SPI SPISEL while it
is master causes an error.
Description
Port D Signals
1-45