MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 62

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2-8
Clock and Timing Signals
Notes:
CLKIN
DLL: Delay Lock Loop
SCC DF: SCC Division Factor
CPM DF: CPM Division Factor
BRG DF: Baud Rate Generator Division Factor
CKO DF: CLKOUT Division Factor
CPLL PDF: Core PLL Pre-Division Factor
CPLL MF: Core PLL Multiplication Factor
1.
2.
3.
4.
5.
6.
Key:
SPLL PDF: System PLL Pre-Division Factor
SPLL MF: System PLL Multiplication Factor
Bus DF: Bus Division Factor
SPLL
PDF
SPLL PDF is determined by the clock configuration mode.
SPLL MF is determined by the clock configuration mode.
The Bus DF = CLKOUT DF and is 4 or 5 as determined by the clock configuration mode.
SCC DF is always 4.
CPM DF is always 2.
BRG DF is set by the System Clock Control Register (SCCR) and is 4, 16 (default), 64, or 256.
SPLL
MF
2 f
CPM
Figure 2-1. Clocking Scheme
DLL
MSC8101 Technical Data
2 f
CPM
CPM
SCC
BRG
CKO
Bus
DF
DF
DF
DF
DF
BCLK, BCLK_90
SCLK, SCLK_90
CPMCLK, CPMCLK_90
BRGCLK
SC140 Core Clock
CPLL
PDF
CPLL
MF
CLKOUT