MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 70

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MSC8101DS

Manufacturer Part Number
MSC8101DS
Description
MSC8101 Network Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
2-16
PowerPC System Bus Access Timing
Note:
Number
32a
32b
33a
33b
31
34
35
Output specifications are measured from the 1.4 V level of the CLKIN rising edge to the TTL signal level (0.8 or
2.0 V).
PSDVAL/TEA/TA delay from CLKIN rising edge
Address bus/Address attributes/GBL delay from CLKIN rising edge
BADDR delay from CLKIN rising edge
Data bus delay from CLKIN rising edge
DP delay from CLKIN rising edge
Memory controller signals/ALE delay from CLKIN rising edge
All other signals delay from CLKIN rising edge
Address bus/Address attributes/GBL
AACK/ARTRY/TA/TEA/DBG/BG/BR
Table 2-14. AC Characteristics for SIU Outputs
Memory controller/ALE
Characteristic
PSDVAL/TEA/TA
All other outputs
All other inputs
MSC8101 Technical Data
Figure 2-5. Bus Signals
DATA bus
DP output
Data bus
DP input
BADDR
CLKIN
11
12
14
15
32a
32b
33a
33b
34
35
31
Maximum
10
8.5
8.5
5.5
10
10
10
10
9
6
10
Minimum
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Units
ns
ns
ns
ns
ns
ns
ns

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