MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 38

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

1-32
Port B Signals
General-
Purpose
PB20
PB19
PB18
I/O
FCC2: RXD1
MII and HDLC nibble
SI1 TDMA1: L1TXD1
TDM nibble
SI2 TDMD2: L1RSYNC
TDM serial
FCC2: RXD2
MII and HDLC nibble
I
FCC2: RXD3
MII and HDLC nibble
I
2
2
C: SDA
C: SCL
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-8. Port B Signals (Continued)
MSC8101 Technical Data
Direction
Dedicate
Output
Output
Output
Input/
Input/
d I/O
Data
Input
Input
Input
Input
FCC2: MII and HDLC Nibble: Receive Data Bit 1
RXD[0–3] is supported by MII and HDLC nibble mode in
FCC2. RXD3 is the most significant bit. RXD0 is the least
significant bit.
Time-Division Multiplexing A1: Nibble Layer 1 Transmit
Data Bit 1
In the TDMA1 interface supported by SI1. TDMA1 supports
bit and nibble modes. L1TXD3 is the most significant bit.
L1TXD0 is the least significant bit in nibble mode. TDMA1
transmits nibble data out of L1TXD[0–3].
Time-Division Multiplexing D2: Layer 1 Receive
Synchronize Data
In the TDMD2 interface supported by SI2, this is the
synchronizing signal for the receive channel.
FCC2: MII and HDLC Nibble Receive Data Bit 2
RXD[0–3] is supported by MII and HDLC nibble mode in
FCC2. RXD3 is the most significant bit. RXD0 is the least
significant bit.
I
The I
and serial clock (SDA). The I
synchronous, multimaster bus that can connect several
integrated circuits on a board. Clock rates run up to
520 kHz@25 MHz system clock.
FCC2: MII and HDLC Nibble Receive Data Bit 3
RXD[0–3] is supported by MII and HDLC nibble mode in
FCC2. RXD3 is the most significant bit. RXD0 is the least
significant bit.
I
The I
and serial clock (SDA). The I
synchronous, multimaster bus that can connect several
integrated circuits on a board. Clock rates run up to
520 kHz@25 MHz system clock.
2
2
C: Inter-Integrated Circuit Serial Data
C: Inter-Integrated Circuit Serial Clock
2
2
C interface comprises two signals: serial data (SDA)
C interface comprises two signals: serial data (SDA)
Description
2
2
C controller uses a
C controller uses a