MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 7
MSC8101DS
Manufacturer Part Number
MSC8101DS
Description
MSC8101 Network Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1.MSC8101DS.pdf
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Chapter 1
Signal/Connection Descriptions
The MSC8101 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and
Figure 1-2. Table 1-1 lists the functional groups, the number of signal connections in each group, and
references the table that gives a detailed listing of multiplexed signals within each group. Figure 1-1 shows
MSC8101 external signals organized by function. Figure 1-2 indicates how the parallel input/output (I/O)
ports signals are multiplexed. Because the parallel I/O design supported by the MSC8101 Communications
Processor Module (CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins
are not numbered sequentially.
Power (V
Clock
Reset, Configuration, and EOnCE
PowerPC System Bus, HDI16, and Interrupts
Memory Controller
Communications Processor Module (CPM)
Input/Output Parallel Ports
JTAG Test Access Port
Reserved (denotes connections that are always reserved)
CC
, V
DD
, and GND)
Functional Group
Table 1-1. MSC8101 Functional Signal Groupings
MSC8101 Technical Data
Port C
Port D
Port A
Port B
Connections
Number of
Signal
133
80
11
27
26
14
18
5
6
8
5
Table 1-10 on page 1-43
Table 1-11 on page 1-48
Table 1-12 on page 1-48
Table 1-6 on page 1-16
Table 1-7 on page 1-19
Table 1-8 on page 1-28
Table 1-9 on page 1-33
Table 1-2 on page 1-4
Table 1-3 on page 1-5
Table 1-4 on page 1-6
Table 1-5 on page 1-8
Detailed Description
1-1
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