MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 66

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.5.2.1.2 Host Reset Configuration
Host reset configuration allows the host to program the reset configuration word via the Host port after
PORESET
the signals described in Table 2-10 one the rising edge of
If HPE is sampled high, the host port is enabled. In this mode the
extends the internal
write four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration
word, which is 32 bits wide. For more information, see the MSC8101 Technical Reference Manual. The reset
configuration word is programmed before the internal PLL and DLL in the MSC8101 are locked. The host
must program it after the rising edge of the
that does not depend on the MSC8101 clock. After the PLL and DLL are locked,
another 512 bus clocks and is then released. The
2.5.2.1.3 Hardware Reset Configuration
Hardware reset configuration is enabled if HPE is sampled low at the rising edge of
driven on
configuration. If
configuration slave. If
configuration master. Section 2.5.2.1.3, Hardware Reset Configuration, explains the configuration sequence
and the terms “configuration master” and “configuration slave.”
2-12
Reset Timing
Notes:
No.
6
Delay from SPLL lock to SRESET deassertion
1.
RSTCONF
DLL enabled
— BCLK = 20 MHz
— BCLK = 100 MHz
DLL disabled
— BCLK = 20 MHz
— BCLK = 100 MHz
is deasserted, as described in the MSC8101 Technical Reference Manual. The MSC8101 samples
Value given for lowest possible CLKIN frequency 10 MHz to ensure proper initialization of reset sequence.
RSTCONF
PORESET
while
RSTCONF
Characteristics
PORESET
is deasserted (driven high) while
until the host programs the reset configuration word register. The host must
is asserted (driven low) while
Table 2-11. Reset Timing (Continued)
changes from assertion to deassertion determines the MSC8101
MSC8101 Technical Data
PORESET
SRESET
input. In this mode, the host must have its own clock
PORESET
is released three bus clocks later (see Figure 2-2).
PORESET
PORESET
RSTCONF
3588
515
Expression
when the signal is deasserted.
changes, the MSC8101 acts as a
BCKT
BCKT
changes, the MSC8101 acts as a
pin must be pulled up. The device
C
HRESET
C
PORESET
Min
remains asserted for
179.40
35.88
25.75
5.15
. The value
Max
Unit
s
s
s
s