MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 79

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MSC8101DS

Manufacturer Part Number
MSC8101DS
Description
MSC8101 Network Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
2.5.6
Figure 2-17 shows the signal behavior of the EE pins.
Note:
Number
65
66
EE Signals
1.
2.
3.
EE pins as inputs
EE pins as outputs
GCLK is the DSP core clock. The ratio between the DSP clock and CLKOUT is configured during
power-on-reset. See Table 2-6 on page 2-6.
Direction of the EE pins is configured in the EE_CTRL register of the EOnCE (See the SC140 Core
Reference Manual , MNSC140CORE/D).
Refer to Table 1-4 on page 1-6 for detailed information about EE pin functionality.
EEi, EED out
EEi, EED in
Characteristics
Figure 2-17. EE Pins Timing
Table 2-19. EE Pins Timing
MSC8101 Technical Data
Synchronous to GCLK
Asynchronous
66
65
Type
4 GCLK periods
1 GCLK period
Minimum
EE Signals
2-25

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