MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 64

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.5.2
The MSC8101 has several inputs to the reset logic:
Asserting an external PORESET causes concurrent assertion of an internal PORESET signal, HRESET, and
SRESET. When the external PORESET signal is deasserted, the MSC8101 samples several configuration
pins:
All these reset sources are fed into the reset controller, which takes different actions depending on the source of
the reset. The reset status register indicates the last sources to cause a reset. Table 2-9 describes reset causes.
2.5.2.1 Reset Operation
The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate
logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are
initialized only on hard reset. Soft reset initializes the internal logic while maintaining the system
configuration. The MSC8101 has two mechanisms for reset configuration: host reset configuration and
hardware reset configuration.
2.5.2.1.1 Power-On Reset Flow
Asserting the
externally for at least 16 input clock cycles after external power to the MSC8101 reaches at least 2/3 V
Table 2-10 shows, the MSC8101 has five configuration pins, four of which are multiplexed with the SC140
core EONCE Event (EE[0–1], EE[4–5]) pins and the fifth of which is the
sampled at the rising edge of
sampled by the MSC8101. The signals on these pins and the MODCK_H value in the Hard Reset
Configuration Word determine the PLL locking mode, by defining the ratio between the DSP clock, the bus
clocks, and the CPM clock frequencies.
2-10
Reset Timing
Power-on reset
(PORESET)
Hard reset
(HRESET)
Soft reset
(SRESET)
Name
External hard reset (HRESET)
External soft reset (SRESET)
RSTCONF—determines whether the MSC8101 is a master (0) or slave (1) device
Power-on reset (PORESET)
DBREQ—determines whether to operate in normal mode (0) or invoke the SC140 debug mode (1)
HPE—disable (0) or enable (1) the host port (HDI16)
BTM[0–1]—boot from external memory (00) or the HDI16 (01)
Reset Timing
PORESET
Input/Output
Input/Output
Direction
Input
external pin initiates the power-on reset flow.
PORESET
PORESET initiates the power-on reset flow that resets all the MSC8101s and
configures various attributes of the MSC8101, including its clock mode.
The MSC8101 can detect an external assertion of HRESET only if it occurs
while the MSC8101 is not asserting reset. During HRESET, SRESET is
asserted. HRESET is an open-drain pin.
The MSC8101 can detect an external assertion of SRESET only if it occurs
while the MSC8101 is not asserting reset. SRESET is an open-drain pin.
. In addition to these configuration pins, three (
MSC8101 Technical Data
Table 2-9. Reset Causes
Description
PORESET
RSTCONF
should be asserted
pin. These pins are
MODCK[1–3]
) pins are
CC
. As