MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 45

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

General-
Purpose
PC13
PC12
I/O
SI1: L1ST4
SCC2: CTS,CLSN
FCC1:TXADDR1
UTOPIA master
FCC1: TXADDR1
UTOPIA slave
SI1: L1ST3
SCC2: CD, RENA
FCC1: RXADDR1
UTOPIA master
FCC1: RXADDR1
UTOPIA slave
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-9. Port C Signals (Continued)
d I/O Data
Direction
Dedicate
Output
Output
Output
Output
Input
Input
Input
Input
MSC8101 Technical Data
Serial Interface 1: Layer 1 Strobe 4
In the time-slot assigner supported by SI1. The MSC8101 time-slot
assigner supports up to four strobe outputs that can be asserted on
a bit or byte basis. The strobe outputs are useful for interfacing to
other devices that do not support the multiplexed interface or for
enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms
for such applications as stepper-motor control.
SCC2: Clear to Send, Collision
Typically used in conjunction with RTS. The MSC8101 SCC2
transmitter sends out a request to send data signal (RTS). The
request is accepted when CTS is returned low. CLSN is the signal
used in Ethernet mode. See also PC28.
FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 1
In the ATM UTOPIA master interface supported by FCC1, this is
transmit address bit 1.
FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 1
In the ATM UTOPIA slave interface supported by FCC1, this is
transmit address bit 1.
Serial Interface 1: Layer 1 Strobe 3
In the time-slot assigner supported by SI1. The MSC8101 time-slot
assigner supports up to four strobe outputs that can be asserted on
a bit or byte basis. The strobe outputs are useful for interfacing to
other devices that do not support the multiplexed interface or for
enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms
for such applications as stepper-motor control.
SCC2: Carrier Detect, Request Enable
Typically used in conjunction with RTS supported by SCC2. The
MSC8101 SCC2 transmitter requests to the receiver that it sends
data by asserting RTS low. The request is accepted when CTS is
returned low.
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 1
In the ATM UTOPIA master interface supported by FCC1, this is
receive address bit 1.
FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 1
In the ATM UTOPIA slave interface supported by FCC1, this is
receive address bit 1.
Description
Port C Signals
1-39