MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 26

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

1-20
Port A Signals
PA30
PA29
General-
Purpose
I/O
FCC1: TXCLAV
UTOPIA slave
FCC1: TXCLAV
UTOPIA master , or
FCC1: TXCLAV0
UTOPIA master, Multi-PHY,
direct polling
FCC1: RTS
HDLC, Serial and Nibble
FCC1: CRS
MII
FCC1: TXSOC
UTOPIA master
FCC1: TXSOC
UTOPIA slave
FCC1: TX_ER
MII
Peripheral Controller:
Dedicated Signal
Name
Protocol
Table 1-7. Port A Signals (Continued)
MSC8101 Technical Data
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Input
Input
Input
Input
FCC1: UTOPIA Slave Transmit Cell Available
In the ATM UTOPIA interface supported by FCC1, TXCLAV is
asserted by the MSC8101 (UTOPIA slave PHY) when the
MSC8101 can accept one complete ATM cell.
FCC1: UTOPIA Master Transmit Cell Available
In the ATM UTOPIA interface supported by FCC1, TXCLAV is
asserted by an external UTOPIA slave PHY to indicate that it
can accept one complete ATM cell.
FCC1: UTOPIA Master Transmit Cell Available Multi-PHY
Direct Polling
In the ATM UTOPIA interface supported by FCC1, TXCLAV0
is asserted by an external UTOPIA slave PHY using direct
polling to indicate that it can accept one complete ATM cell.
FCC1: Request To Send
In the standard modem interface signals supported by FCC1
(RTS, CTS, and CD). RTS is asynchronous with the data. RTS
is typically used in conjunction with CD. The MSC8101 FCC1
transmitter requests the receiver to send data by asserting
RTS low. The request is accepted when CTS is returned low.
FCC1: Media Independent Interface Carrier Sense
In the MII interface supported by FCC1. CRS is asserted by an
external fast Ethernet PHY. It indicates activity on the cable.
FCC1: UTOPIA Transmit Start of Cell
In the ATM UTOPIA interface supported by FCC1. TXSOC is
asserted by the MSC8101 (UTOPIA master PHY) when
TXD[0–7] contains the first valid byte of the cell.
FCC1: UTOPIA Transmit Start of Cell
In the ATM UTOPIA interface supported by FCC1. TXSOC is
asserted by the external UTOPIA master PHY when TXD[0–7]
contains the first valid byte of the cell.
FCC1: Media Independent Interface Transmit Error
In the MII interface supported by FCC1. TX_ER is asserted by
the MSC8101 to force propagation of transmit errors.
Description