S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 24

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

2.10 ATPG (Auto Test-Pattern Generation)
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
(1) Introduction
(2) Outline
ATPG refers to automatic pattern generation, for which tools are released from each tool
vendor. Testgen from Synopsys is used for ASIC design by Seiko Epson. Use of Testgen
helps to automatically generate a test pattern following the insertion of scan circuits into the
original circuit.
The word “control” as used in this manual means that any level can be applied to the target
pin without being routed via a sequential circuit. That is, it does not refer to clocks, such as
divided-by-N clocks, that require several cycles for status settings. For example, the
description, “Each flip-flop can have its clock controlled from the outside” refers to a circuit
in which an external input clock (clocking source) can reach each flip-flop.
Scan insertion is executed on circuits that conform to the design rules required for ATPG
support, and fault detection by ATPG is performed. In addition, because ATPG tools
operate the internal nodes forcibly from external pins through a scan circuit, the test
patterns output by ATPG tools cannot be used to observe operation of the user circuit.
Therefore, customers are requested to create the test pattern necessary to verify the basic
operation of the circuit. In other words, keep in mind that the test patterns generated by
ATPG tools are used only for the purpose of increasing the fault detection rate. The use of
ATPG tools helps to generate a test pattern that, for full-scan circuits, can attain a high fault
detection rate of close to 100%, except for untestable nodes in which logical fault detection
is impossible. Note that ATPG uses the full-scan method based on MUXSCAN-type flip-
flops.
EPSON
Chapter 2: Precautions on Circuit Design
19