S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 4

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
Chapter 1 Overview.................................................................................................. 1
Chapter 2 Precautions on Circuit Design ............................................................ 10
Chapter 3 Types of Input/Output Buffers and Usage Precautions.................... 33
Chapter 4 Circuit Design Taking Testability into Account................................. 55
Chapter 5 Propagation Delay Time and Timing Design ..................................... 64
1.1 Features........................................................................................................................ 1
1.2 Electrical Characteristics............................................................................................... 2
1.3 Outline of Standard-Cell Development Flow................................................................. 8
2.1 Insertion of Input/Output Buffers ................................................................................. 10
2.2 Use of Differentiating Circuits Inhibited....................................................................... 10
2.3 Wired Logic Inhibited .................................................................................................. 10
2.4 Hazard Protection ....................................................................................................... 11
2.5 Fan-Out Limitations..................................................................................................... 11
2.6 Internal Bus Circuits.................................................................................................... 12
2.7 Bus Hold Circuits ........................................................................................................ 14
2.8 Precautions on Creating Circuit Diagrams (Logic Diagrams) ..................................... 15
2.9 Clock Tree Synthesis .................................................................................................. 15
2.10 ATPG (Auto Test-Pattern Generation)...................................................................... 19
2.11 Limitations and Restrictions on VHDL and Verilog-HDL Netlists .............................. 30
3.1 Types of Input/Output Buffers ..................................................................................... 33
3.2 Input/Output-Buffer Configuration with a Single Power Supply .................................. 35
3.3 Configuration of Oscillator Circuits.............................................................................. 47
3.4 Gated I/O Cells ........................................................................................................... 49
4.1 Consideration for Circuit Initialization.......................................................................... 55
4.2 Consideration for Reduction of the Test-Pattern Size................................................. 55
4.3 Circuit Configuration to Facilitate DC and AC Tests ................................................... 56
4.4 Test Circuit for Functional Cells .................................................................................. 62
5.1 Precautions Regarding the Relationship between Ta and Tj...................................... 64
5.2 Simplified Delay Models.............................................................................................. 65
5.3 Load Due to Input Capacitance (Load A).................................................................... 67
5.4 Load Due to Wiring Capacitance (Load B) ................................................................. 68
5.5 Calculating the Propagation Delay Time..................................................................... 68
2.11.1 Common .......................................................................................................................... 30
2.11.2 Limitations and Restrictions on Verilog-HDL Netlists....................................................... 31
2.11.3 Limitations and Restrictions on VHDL Netlists................................................................. 32
3.1.1 Selecting Input/Output Buffers ........................................................................................... 33
3.2.1 Input/Output-Buffer Configuration with a Single Power Supply ......................................... 35
3.2.2 Fail-Safe Cells.................................................................................................................... 42
3.3.1 When Configuring an Oscillator Circuit .............................................................................. 47
3.3.2 Precautions on the Use of Oscillator Circuits..................................................................... 48
3.4.1 Outline of Gated I/O Cells .................................................................................................. 49
3.4.2 Features of Gated I/O Cells ............................................................................................... 49
3.4.3 Precautions on the Use of Gated I/O Cells ........................................................................ 49
4.3.1 Configuration of a Test Circuit ........................................................................................... 56
4.4.1 Configuration of a Test Circuit ........................................................................................... 62
4.4.2 Test Patterns...................................................................................................................... 62
4.4.3 Test-Circuit Information...................................................................................................... 63
3.2.1.1 Input-Buffer Configuration with a Single Power Supply............................................. 35
3.2.1.2 Output-Buffer Configuration with a Single Power Supply.......................................... 36
3.2.1.3 Bidirectional-Buffer Configuration with a Single Power Supply ................................. 39
S1K50000 Series Table of Contents
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