S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 86

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

6.7 Restrictions on Test Patterns for Bidirectional Pins
6.8 Precautions on Handling of the High-Impedance State
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
Due to tester limitations, bidirectional pins cannot be switched between input and output
modes more than twice within one event. Therefore, in the creation of a test pattern, make
sure it will not use RZ waveforms to control switching between the input and output modes of a
bidirectional cell.
For bidirectional pins, however, RZ waveforms can be used, provided that the pin does not
have an output state and is handled in the same way as an input pin.
At Seiko Epson, the input pins of CMOS devices cannot be in the high-impedance state during
simulation, as device operation cannot be guaranteed.
For high-impedance-related measures, I/O cells with pull-up/down resistors are available from
Seiko Epson. However, for the reasons specified below, propagation delays during simulation
are not taken into consideration for changes in signal state due to the pull-up/down resistors.
Because exact operation cannot be simulated, for I/O cells with pull-up/down resistors
(including bidirectional pins), a non-input state cannot exist in the input mode during
simulation.
<Reasons that propagation delays in pull-up/down resistors are not taken
into consideration>
At Seiko Epson, before simulation is performed, test patterns are checked for the above using
a tool. When the letter “Z,” which represents the high-impedance state, is detected in
bidirectional pins (including those with N-channel open-drain output), customers are requested
to correct the test pattern.
In such a case, if the letter “Z” is detected in bidirectional pins with pull-up/down resistors,
customers will also be requested to correct the test pattern for the reasons described above.
The same applies to bidirectional pins with open-drain output.
• Because the delay fluctuates significantly due to the external load capacitance
• Because the pull-up/down resistors are used only to avoid floating gates caused by the
high-impedance state
EPSON
Chapter 6: Creating Test Patterns
81