S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 79

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 6: Creating Test Patterns
Chapter 6 Creating Test Patterns
6.1 Testability Consideration
6.2 Usable Waveform Modulation
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NR
RZ waveform
Output waveform
Strobe
Upon completion of logic design, create test patterns. Not only are test patterns used for
simulations to verify operation of the designed circuit, they are also used for product inspection
at shipment.
To increase the quality of shipped products, note the following in the creation of a test pattern.
Because test patterns are used for product inspection at shipment, they must be created so as
to allow the entire internal circuit of an LSI to be tested. If any part of the internal circuit of an
LSI remains untested, that part cannot be tested at product shipment, which may result in the
shipment of NG products.
Generally speaking, not all parts of the internal circuit of an LSI can be tested. This requires
that testability be taken into consideration from the circuit design stage.
DC test and various other conditions required for test patterns can be set easily through the
insertion of a Seiko Epson-recommended test circuit. For details, see Section 4.4, “Test
Circuit for Functional Cells.”
A test pattern normally consists of sequences of 0s and 1s. They allow a delay to be inserted
in the input waveform or the waveform itself to be altered during a simulation or testing using
an LSI tester. The following two waveforms can be used in the creation of a test pattern:
Z
• NRZ (Non-Return to Zero)
• RZ (Return to Zero)
This waveform is normally used for signals other than the clock. This waveform can
change state once within a test rate period, making it possible to insert a delay.
This waveform is used primarily for the clock signal. Because this waveform can generate
a positive or negative pulse within one test rate period, it aids in the efficient creation of a
clock signal. It also allows a delay to be inserted, as with NRZ.
Test rate
Figure 6-1 Limitations on Timing Settings
Input delay
EPSON
Waveform
Pulse width
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE