S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 75

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 5: Propagation Delay Time and Timing Design
5.6 Calculating the Output-Buffer Delay Time
5.7 Flip-Flop Setup and Hold Times
70
Letting the load capacitance connected to the output buffer be CL, the delay time tpd is
obtained using the equation shown below.
For details on the nonloaded and loaded delay coefficients of output cells, see the “Standard
Cell S1K50000-Series MSI Cell Library.”
The signal timing applied by flip-flops and an MSI sequential circuit consisting of flip-flops play
an important role in the proper operation of the configured circuit with the intended logic. The
flip-flop’s setup and hold times are closely associated with this signal timing. Data which,
when entered or changed in state, failed to meet the timing requirements regulated by the
setup and hold times cannot be written correctly to the flip-flop circuit. Therefore, the signal
timing must be designed in consideration of these setup and hold times.
(1) Minimum pulse width
(2) Setup time
(3) Hold time
t
In flip-flops and MSIs consisting of flip-flops, this refers to the minimum width of an input
pulse between the leading and trailing edges of its waveform. Pulses applied in widths
smaller than this value are not only ineffective as signals, but may also cause malfunction.
In flip-flops and MSIs consisting of flip-flops, if data is to be read correctly, it must be set to
the valid state before a change in the active clock edge occurs. The time required for it is
referred to as the “setup time.”
In flip-flops and MSIs consisting of flip-flops, if data is to be read correctly, it should be held
in the valid state after the active clock edge is entered. The time required for this is referred
to as the “hold time.”
pd
= T
where T
The following three minimum pulse widths are defined:
0
(output cell) + K (output cell) x C
K (output cell)
C
• Minimum pulse width of a clock signal
• Minimum pulse width of a set signal
• Minimum pulse width of a reset signal
0
L
(output cell)
: nonloaded delay of output cell
: loaded delay coefficient of output cell
: connected load capacitance
EPSON
L
/10
STANDARD CELL S1K50000 SERIES
[ pF ]
[ ps ]
[ ps/10 pF ]
DESIGN GUIDE