S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 32

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
(9) ATPG check sheet
Please be sure to submit this sheet one week prior to data-in. Encircle the appropriate
answer for each question.
Note 1: If Yes, please correct your circuit, as the circuit cannot be scanned.
Note 2: If No, please insert DFT, as the circuit cannot be scanned. In addition, if you would
1. Interface netlist format for Seiko Epson (gate level)
2. Are scan flip-flops used in the original circuit? (Note 1)
3. Is any macro cell, MSI cell, or intermittently oscillating cell used?
4. If Yes, enter the cell name: ____________________________________________
5. Is any internal tri-state bus used?
6. Does any RS latch, differentiating circuit,
7. Are latch cells used?
8. Are bidirectional pins included?
9. Is there any clock that cannot be controlled directly from the outside? Yes
10. Are there any reset/set pins for flip-flops or latch cells
11. If you answered Yes to any of questions 3 through 10 above,
12. Are I/O cells placed at the top level?
13. Are measures taken to correct the skew problems of clock nets
or asynchronous circuit exist?
that cannot be controlled directly from the outside?
is your circuit designed in conformity with the DFT rules? (Note 2)
by Clock Tree Synthesis?
like to request DFT insertion by Seiko Epson because detailed circuit information is
required in addition to this sheet, contact Seiko Epson.
EPSON
Chapter 2: Precautions on Circuit Design
Verilog
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
or
or
or
or
or
or
or
or
or
or
or
or
EDIF
No
No
No
No
No
No
No
No
No
No
No
27