S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 47

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 3: Types of Input/Output Buffers and Usage Precautions
3.2.2 Fail-Safe Cells
42
(1) Outline
(2) Features
(3) Usage precautions
Seiko Epson’s S1K50000 series of Fail-Safe cells allows signals operating at levels higher
than the power-supply voltage in a single-power-supply design to be interfaced without the
installation of a dedicated interfacing power supply. Therefore, it is not necessary for
customers to install the operating power supply or an interfacing power supply in the LSI,
as is conventionally required. In addition, signals operating at levels equal to the power-
supply voltage can also be interfaced without modifying the circuit. This provides
customers with greater freedom in circuit design.
• With no limitations on the number of cells used or their placement, the Fail-Safe cells can
• In a single-power-supply design, signals operating at levels higher than the power-supply
• The supported input levels are the LVTTL and LVTTL Schmitt levels (when V
• Because the Fail-Safe cells are entirely of a CMOS structure, they help to reduce the
• The Fail-Safe cells cannot determine Seiko Epson’s standard input level for reasons of
• The Fail-Safe cells are characterized in that when the output pins are in High-Z state, i.e.,
• Although signals with a voltage level equal to or greater than the LSI’s operating voltage
be placed as desired by customers, providing freedom in circuit design.
voltage can be interfaced from the outside without the installation of a dedicated interfac-
ing power supply equal to or greater than the power-supply voltage.
as well as the CMOS and CMOS Schmitt levels (when V
chip’s power consumption.
circuit configuration. Therefore, if it is necessary for the input level to be determined by a
tester, a test circuit must be configured separately. In such a case, refer to the example
of a test circuit on page 54 (Figure 3-6) in the creation of a test circuit.
in input mode, no DC current will flow into the LSI even when signals exceeding the
power-supply voltage are fed into the pins. However, if signals equal to or greater than
the power-supply voltage are fed into the pins when the cell is in output mode and output-
ting a high-level signal, DC current will flow into the LSI as with a conventional Fail-Safe
cell. This occurs in a situation in which, while the Fail-Safe cell is outputting a high-level
(3.3 V) signal, another device is also outputting a high-level (5.0 V) signal at the same
time. Note that the other device referred to here includes a pull-up resistor.
can be accepted, in no case can the signal voltages applied to the Fail-Safe cell exceed
the Absolute Maximum Rated Voltage.
EPSON
DD
= 2.0 V).
STANDARD CELL S1K50000 SERIES
DD
DESIGN GUIDE
= 3.3 V),