S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 36

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

2.11.2 Limitations and Restrictions on Verilog-HDL Netlists
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
(7) Descriptions using assign and tran in gate-level Verilog netlists are prohibited.
(8) For connecting descriptions in Verilog netlists, connections using the pin names of cells
(9) Verilog commands such as force cannot be used in the operational description of flip-
(10) A time-scale description must be added at the beginning of gate-level netlists generated
(11) Seiko Epson prohibited the mixed use of a bus’ single port and the name escaped by
(12) The strings listed below are Verilog’s reserved words. Use of these strings as user-
are recommended.
Examples: Pin-name connection: IN2 inst_1 (.A(inst_2),.X(inst_3)); recommended
flops.
(Example: logic.signal = 0;)
by a Synopsys design compiler. This time scale must have the same value as that
specified in the Seiko Epson Verilog library. For the time scales in each series, see (6).
Example: `timescale 1 ps / 1 ps
attaching _\_ to that port within the same module, as follows:
input A[0];
wire \A[0] ;
defined names is prohibited.
always, and, assign, begin, buf, bufif0, bufif1, case, design,default, defparam, disable,
else, end, endcase, endfunction, endmodule, endtask, event, for, force, forever, fork,
function, highz0, highz1, if, initial, inout, input, integer, join, large, medium, module, nand,
negedge, nor, not, notif0, notif1, or, output, parameter, posedge, pull0, pull1, reg, release,
repeat, scalared, small, specify, strong0, strong1, supply0, supply1, task, time, tri, tri0,
tri1, trinand, trior, trireg, vectored, wait, wand, weak0, weak1, while, wire, wor, xor, xnor
Net-name connection: IN2 inst_1 (net1,net2);
EPSON
Chapter 2: Precautions on Circuit Design
31