UPD78F0138 NEC, UPD78F0138 Datasheet - Page 164

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

164
Cautions 1. Values in the following range should be set in CR00n and CR01n:
Remark ×: Don’t care
TOC0n
PRM0n
TMC0n
CRC0n
ES1n1
n = 0:
n = 0, 1:
0/1
2. The cycle of the pulse generated through PPG output (CR00n setting value + 1) has a duty of
7
0
7
0
7
0
0000H ≤ CR01n < CR00n ≤ FFFFH
(CR01n setting value + 1)/(CR00n setting value + 1).
OSPT0n
ES1n0
0/1
0
6
0
6
0
µ
µ
PD780131, 780132
PD780133, 780134, 78F0134, 780136, 780138, 78F0138
Figure 6-18. Control Register Settings for PPG Output Operation
OSPE0n
ES0n1
0/1
0
5
0
5
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
TOC0n4
ES0n0
(c) 16-bit timer output control register 0n (TOC0n)
(a) 16-bit timer mode control register 0n (TMC0n)
(b) Capture/compare control register 0n (CRC0n)
0/1
1
4
0
4
0
LVS0n
(d) Prescaler mode register 0n (PRM0n)
TMC0n3
0/1
1
3
0
3
0
LVR0n
TMC0n2
CRC0n2
0/1
User’s Manual U16228EJ2V0UD
1
0
0
2
TOC0n1
TMC0n1
CRC0n1 CRC0n0
PRM0n1
1
0/1
0
TOE0n
OVF0n
PRM0n0
1
0/1
0
0
Enables TO0n output.
Inverts output on match between TM0n and CR00n.
Specifies initial value of TO0n output F/F (setting “11” is prohibited).
Inverts output on match between TM0n and CR01n.
Disables one-shot pulse output.
Clears and starts on match between TM0n and CR00n.
CR00n used as compare register
CR01n used as compare register
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)