UPD78F0138 NEC, UPD78F0138 Datasheet - Page 186

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

(8) Timer operation
(9) Capture operation
(10) Compare operation
(11) Edge detection
186
<1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit timer capture/compare
<2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI00n/TI01n pins
<3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
<1> If TI00n valid edge is specified as the count clock, a capture operation by the capture register specified as
<2> To ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than
<3> The capture operation is performed at the falling edge of the count clock. An interrupt request input
A capture operation may not be performed for CR00n/CR01n set in compare mode even if a capture trigger has
been input.
<1> If the TI00n or TI01n pin is high level immediately after system reset and the rising edge or both the rising
<2> The sampling clock used to remove noise differs when the TI00n valid edge is used as the count clock and
register 01n (CR01n).
are not acknowledged.
clear & start occurs at the TI00n valid edge. In the mode in which clear & start occurs on a match between
the TM0n register and CR00n register, one-shot pulse output is not possible because an overflow does not
occur.
the trigger for TI00n is not possible.
the count clock selected by prescaler mode register 0n (PRM0n).
(INTTM00n/INTTM01n), however, is generated at the rise of the next count clock.
and falling edges are specified as the valid edge of the TI00n or TI01n pin to enable the 16-bit timer counter
0n (TM0n) operation, a rising edge is detected immediately after the operation is enabled. Be careful
therefore when pulling up the TI00n or TI01n pin. However, the rising edge is not detected at restart after
the operation has been stopped once.
when it is used as a capture trigger. In the former case, the count clock is f
count clock is selected by prescaler mode register 0n (PRM0n). The capture operation is started only after
a valid edge is detected twice by sampling, thus eliminating noise with a short pulse width.
Remark n = 0:
n = 0, 1:
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
µ
µ
PD780131, 780132
PD780133, 780134, 78F0134, 780136, 780138, 78F0138
User’s Manual U16228EJ2V0UD
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, and in the latter case the