UPD78F0138 NEC, UPD78F0138 Datasheet - Page 246

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

(4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (f
10.4.4 Watchdog timer operation in HALT mode (when “Ring-OSC can be stopped by software” is selected by
X1 input clock (f
timer is the X1 input clock (f
the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds its value.
246
The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the
CPU operation
CPU operation
instruction execution
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Watchdog timer
Watchdog timer
mask option)
Figure 10-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock)
XP
f
f
f
XP
XT
XP
f
f
R
R
), Ring-OSC clock (f
Normal operation
Normal operation
(Ring-OSC clock)
Operating
Operating Operation stopped
XP
) or Ring-OSC clock (f
Operation stopped
Oscillation
stopped
Figure 10-8. Operation in HALT Mode
HALT
STOP
R
), or subsystem clock (f
CHAPTER 10 WATCHDOG TIMER
User’s Manual U16228EJ2V0UD
Clock supply stopped
R
Oscillation stabilization time
). After HALT mode is released, counting is started again using
(set by OSTS register)
17 clocks
Operating
XT
), or whether the operation clock of the watchdog
Normal operation
Normal operation (Ring-OSC clock)
Operating
R
) during STOP