UPD78F0138 NEC, UPD78F0138 Datasheet - Page 338

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

338
Address: FF89H After reset: 00H R/W
CSIC11
Cautions 1. When the Ring-OSC clock is selected as the clock supplied to the CPU, the clock of the Ring-
Remarks 1. Figures in parentheses are for operation with fx = 10 MHz
Symbol
2. f
2. Do not write to CSIC11 while CSIE11 = 1 (operation enabled).
3. Clear CKP11 to 0 to use P02/SO11, P03/SI11, and P04/SCK11 as general-purpose port pins.
4. The phase type of the data clock is type 1 after reset.
CKS112
CKP11
X
OSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial
interface CSI11 is not guaranteed.
: X1 input clock oscillation frequency
7
0
0
0
1
1
0
0
0
0
1
1
1
1
Figure 15-6. Format of Serial Clock Selection Register 11 (CSIC11)
CKS111
DAP11
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11
6
0
0
1
0
1
0
0
1
1
0
0
1
1
CKS110
SI11 input timing
SI11 input timing
SI11 input timing
SI11 input timing
5
0
0
1
0
1
0
1
0
1
User’s Manual U16228EJ2V0UD
Specification of data transmission/reception timing
SCK11
SCK11
SCK11
SCK11
f
f
f
f
f
f
f
External clock input to SCK11
SO11
SO11
X
X
X
X
X
X
X
SO11
SO11
/2 (5 MHz)
/2
/2
/2
/2
/2
/2
CKP11
2
3
4
5
6
7
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(312.5 kHz)
(156.25 kHz)
(78.13 kHz)
4
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSI11 serial clock selection
DAP11
3
CKS112
2
CKS111
1
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
CKS110
Mode
Type
0
1
2
3
4