UPD78F0138 NEC, UPD78F0138 Datasheet - Page 462

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

462
Bit
manipulate
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
AND1
OR1
XOR1
SET1
CLR1
SET1
CLR1
NOT1
Mnemonic
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW. bit
CY, [HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Operands
CHAPTER 28 INSTRUCTION SET
User’s Manual U16228EJ2V0UD
Bytes
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
2
3
2
2
2
2
3
2
2
2
1
1
1
Note 1
6
−
4
−
6
6
−
4
−
6
6
−
4
−
6
4
−
4
−
6
4
−
4
−
6
2
2
2
Clocks
8 + n + m (HL).bit ← 1
8 + n + m (HL).bit ← 0
Note 2
7 + n
7 + n
7 + n
7
7
−
7
7
7
−
7
7
7
−
7
6
8
−
6
6
8
−
6
−
−
−
CY ← CY ∧ saddr.bit)
CY ← CY ∧ sfr.bit
CY ← CY ∧ A.bit
CY ← CY ∧ PSW.bit
CY ← CY ∧ (HL).bit
CY ← CY ∨ (saddr.bit)
CY ← CY ∨ sfr.bit
CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
CY ← CY ∨ (HL).bit
CY ← CY ∨ (saddr.bit)
CY ← CY ∨ sfr.bit
CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
CY ← CY ∨ (HL).bit
(saddr.bit) ← 1
sfr.bit ← 1
A.bit ← 1
PSW.bit ← 1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit ← 0
PSW.bit ← 0
CY ← 1
CY ← 0
CY ← CY
CPU
) selected by the processor clock
Operation
Z AC CY
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
0
×