UPD78F0138 NEC, UPD78F0138 Datasheet - Page 464

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

464
Conditional
branch
CPU
control
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
BT
BF
BTCLR
DBNZ
SEL
NOP
EI
DI
HALT
STOP
Mnemonic
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
C, $addr16
Saddr, $addr16
RBn
Operands
CHAPTER 28 INSTRUCTION SET
User’s Manual U16228EJ2V0UD
Bytes
3
4
3
3
3
4
4
3
4
3
4
4
3
4
3
2
2
3
2
1
2
2
2
2
Note 1
10
10
10
10
10
8
−
8
−
−
8
−
−
8
−
6
6
8
4
2
−
−
6
6
Clocks
12 + n + m PC ← PC + 3 + jdisp8 if (HL).bit = 1
Note 2
11 + n
11 + n
11
11
11
11
12
12
12
10
9
−
9
−
−
−
−
−
−
6
6
−
−
PC ← PC + 3 + jdisp8 if(saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 3 + jdisp8 if PSW.bit = 1
PC ← PC + 3 + jdisp8 if (HL).bit = 1
PC ← PC + 4 + jdisp8 if(saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW. bit = 0
PC ← PC + 3 + jdisp8 if (HL).bit = 0
PC ← PC + 4 + jdisp8
if(saddr.bit) = 1
then reset(saddr.bit)
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
then reset (HL).bit
B ← B − 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C −1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if(saddr) ≠ 0
RBS1, 0 ← n
No Operation
IE ← 1(Enable Interrupt)
IE ← 0(Disable Interrupt)
Set HALT Mode
Set STOP Mode
CPU
) selected by the processor clock
Operation
Z AC CY
×
Flag
×
×