UPD78F0138 NEC, UPD78F0138 Datasheet - Page 270
UPD78F0138
Manufacturer Part Number
UPD78F0138
Description
(UPD78xxxx) 8-Bit Single-Chip Microcontrollers
Manufacturer
NEC
Datasheet
1.UPD78F0138.pdf
(558 pages)
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(11) A/D converter sampling time and A/D conversion start delay time
Note The A/D conversion start delay time is the time after wait period. For the wait function, see CHAPTER 34
Remark f
(12) Register generating wait cycle
270
FR2
Sampling timing
0
0
0
1
1
1
The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM).
The delay time exists until actual sampling is started after A/D converter operation is enabled.
When using a set in which the A/D conversion time must be strictly observed, care is required for the contents
shown in Figure 12-21 and Table 12-3.
Do not read data from the ADCR register and do not write data to the ADM, ADS, PFM, and PFT registers while
the CPU is operating on the subsystem clock and while oscillation of the clock input to X1 is stopped.
Other than above
CAUTIONS FOR WAIT.
Table 12-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)
X
INTAD
FR1
ADCS
: X1 clock oscillation frequency
0
0
1
0
0
1
Figure 12-21. Timing of A/D Converter Sampling and A/D Conversion Start Delay
ADCS
FR0
0
1
0
0
1
0
1 or ADS rewrite
288/f
240/f
192/f
144/f
120/f
96/f
Setting prohibited
period
Wait
X
X
X
X
X
X
conversion
start delay
Conversion Time
A/D
time
CHAPTER 12 A/D CONVERTER
User’s Manual U16228EJ2V0UD
Sampling
time
Conversion time
40/f
32/f
24/f
20/f
16/f
12/f
Sampling Time
X
X
X
X
X
X
−
32/f
28/f
24/f
16/f
14/f
12/f
A/D Conversion Start Delay Time
X
X
X
X
X
X
MIN.
−
Sampling
Conversion time
time
36/f
32/f
28/f
18/f
16/f
14/f
X
X
X
X
X
X
MAX.
−
Note
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