UPD78F0138 NEC, UPD78F0138 Datasheet - Page 243

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask option
the watchdog timer mode register (WDTM) = 1, 1, 1).
timer operation in STOP mode and 10.4.4 Watchdog timer operation in HALT mode.
The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the X1 input clock.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
The following shows the watchdog timer operation after reset release.
1.
2.
3.
Notes 1.
Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
For the watchdog timer operation during STOP mode and HALT mode in each status, refer to 10.4.3 Watchdog
The status after reset release is as follows.
• Operation clock: Ring-OSC clock oscillation frequency (f
• Cycle: f
• Counting starts
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
• Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Ring-OSC clock (f
X1 input clock (f
Watchdog timer operation stopped
2.
3.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0 but holds its value.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values.
If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×, respectively, an internal
reset signal is not generated even if the following processing is performed.
• WDTM is written a second time.
• A 1-bit memory manipulation instruction is executed to WDTE.
• A value other than ACH is written to WDTE.
Notes 1, 2, 3
R
/2
18
(1.09 seconds: At operation with f
.
XP
R
)
)
CHAPTER 10 WATCHDOG TIMER
User’s Manual U16228EJ2V0UD
R
= 240 kHz (TYP.))
R
)
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