MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 113

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Bit
4
3
2
1
0
MFREFR
TxSYNC
Name
REFR
JTS
FSI
(0)
(0)
(0)
(0)
(0)
Fs Bit Include. Only applicable in D4 mode. Setting this bit causes errored Fs bits to be included
as framing bit errors. A bad Fs bit will increment the Framing Error Bit Counter, and will
potentially cause a reframe. The Fs bit of the receive frame 12 will only be included if D4SECY is
set. Note that when FSI bit is set both Ft and Fs are taken into consideration before declaration
of synchronization
Reframe. A 0 to 1 transition of this bit causes an automatic reframe.
MultiFrame Reframe. Only applicable in D4 mode. Setting this bit causes an automatic
multiframe reframe. The signaling bits are frozen until multiframe synchronization is achieved.
Terminal frame synchronization is not affected.
Japan Telecom Synchronization. If this bit is set, the S-bit is included in the CRC6 calculation
for the ESF framing Mode.
Transmit Synchronization. Setting this bit causes the transmit multiframe boundary to be
internally synchronized to the incoming S-bits on DSTi channel 31 bit 0.
Table 64 - Framing Mode Select (R/W Address Y00) (T1)
Functional Description
MT9072
113