MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 124

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
124
15-14
13-11
15-11
7-3
2-0
Bit
7-3
2-0
Bit
10
10
9
8
9
8
RxTS4 - 0 Receive Timeslot. A five bit counter that indicates the number of timeslots between the
RxBC2 - 0 Receive Bit Count. A three bit counter that indicates the number of ST-BUS bit times
TxSBMSB
TxBC2 - 0
TxTS4 - 0
RSLPD
RxSLIP
RxFRM
Name
TSLPD
PI2-0
Name
TSLIP
#
#
not used.
Phase Indicator Bits (PI2 to PI0). These bits make up 3 least significant bits of a 12 bit
word which indicate the delay through the receive slip buffer. The delay through the slip
buffer in 2.048 Mhz bit cells is ( 512 - Phase Indicator bits). The delay to DSTo from the
write into the slip buffer is ( 512 - Phase Indicator bits) + 16 bits. These bits are updated
when the slip buffer write address is 0. These 3 bits will reflect the 1/2,1/4 and 1/8
fractions of the Phase Indicator Bits.
Receive Slip Direction. If one, indicates that the last received frame slip resulted in a
repeated frame, i.e., the system clock (C4b) is faster than network clock (EXCLi). If zero,
indicates that the last received frame slip resulted in a lost frame, i.e., system clock slower
than network clock. Updated on an RSLIP occurrence basis.
Receive Slip. A change of state (i.e. 1-to-0 one 0-to-1) indicates that a receive controlled
frame slip has occured.
Receive Frame. The most significant bit of the phase status word. If one, the delay
through the receive elastic buffer is greater than one frame in length; if zero, the delay
through the receive elastic buffer is less than one frame in length.
receive elastic buffer internal write frame boundary and the ST-BUS read frame boundary.
The count is updated every 250 uS.
there are between the receive elastic buffer internal write frame boundary and the ST-BUS
read frame boundary. The count is updated every 250 uS.
not used.
Transmit Slip. A change of state (i.e., 1-to-0 or 0-to-1) indicates that a transmit controlled
frame slip has occurred in the transmitter.
Transmit Slip Direction. If one, indicates that the last transmit frame slip resulted in a
repeated frame, i.e., the internally generated 1.544 MHz. transmit clock is faster than the
system clock (C4b). If zero, indicates that the last transmit frame slip resulted in a lost
frame, i.e., the internally generated 1.544 MHz. transmit clock is slower than network
clock. Updated on an TSLIP occurrence.
Transmit Slip Buffer MSB. The most significant bit of the Transmit Slip Buffer Delay
Word. If one, the delay through the transmit elastic buffer is greater than one frame in
length; if zero, the delay through the transmit elastic buffer is less than one frame in
length. This bit is reset whenever Transmit Set Delay Bits (register address YF7) - are
written to.
Transmit timeslot. A five bit counter that indicates the number of ST-BUS timeslots
between the transmit elastic buffer ST-BUS write frame boundary and the internal
transmit read frame boundary. The count is updated every 250 uS.
Transmit Bit Count. A three bit counter that indicates the number of ST-BUS bit times
there are between the transmit elastic buffer ST-BUS write frame boundary and the
internal read frame boundary. The count is updated every 250 uS.
Table 84 - Transmit Slip Buffer Status Word(Y14) (T1)
Table 83 - Receive Slip Buffer Status Word(Y13) (T1)
Functional Description
Functional Description
Advance Information