MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 148

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MT9072

Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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MT9072
16.1.9
The Global Control and Status Registers are common to the T1 and E1 operation. The global registers are
accessed by address hex 9xx ( A
148
13-5
15-11
3-1
Bit
15
14
10-8
7-6
4-2
4
0
Bit
5
1
0
Global Control and Status Registers (900 - 91F) Bit Functions
STBUS
Name
RSTC
CHANNUM
T1E0
CK1
STBUFEN
CONTSIN
STRNUM
(1)
(0)
(0)
(0)
(00000)
(00000)
#
#
FNUM
Name
CHUP
(000)
(2:0)
(0)
(0)
(0)
#
T1E0. This bit determines if the chip will operate in T1 or E1 mode for all 8 framers. If the value
of this bit is changed the chip is reset in E1 or T1 default register mode. If the bit is set to 1, all
the framer register values are set to T1 defaults. For a setting of 0 the register values are set to
E1 defaults. This action takes approximately 34 1.5444 clock cycles. Hence any writes to
registers should be done on the next 125 usec frame after setting or clearing this bit.
ST-BUS Enable. If zero, ST-BUS timing is enabled. If one, GCI timing is enabled (only
available for 2.048Mb/s mode). See Figures 24-31.
not used.
Clock Rate. This clock select bit determines the system clock at the CKi pin and the receive
frame pulse at the FPi pin as follows (See Figures 24 to 31):
CK1
0
1
not used.
Common Reset. When this bit is changed from zero to one, all eight framers will reset to their
default T1 mode. This software reset has the same effect as the RESET pin. See the Reset
Operation section for the default settings.
Table 123 - Global Control0 Register (R/W Address 900) (T1)
Table 124 - Global Control1 Register (R/W Address 901) (T1)
Channel Number.These 5 bits determine the channel that is used for updating of the ST-
Bus Analyzer buffer.
not used.
Stream Number. These 5 bits determine the streams that will be used as the source data
for the ST-Bus Analyzer buffer.
00: DSTi
01: DSTo
10: CSTi
11: CSTo
ST-BUS Analyser Buffer Enable. Setting this bit enables the ST-BUS Analyser Buffer
update. When the user reads the buffer (920-93F), this bit must be 0. Any reads of the
buffer while this bit is set does not ensure correct data being read.
Framer Number 0 to 7
Channel Update. If 0 the update of the memory is at frame rate for a given channel. The
channel selected for update is provided by the ChanNum bits of this register. If set the
complete frame (channels 0 to 32) are updated to the buffer.
Continuous Single. If set to 1 the ST-BUS Analyzer buffer is updated continuously. If set
to zero the buffer is updated once and stopped. An optional interrupt can be generated
once the buffer is full.
11
Clock
4.096MHz
16.384MHz
and A
8
being high and A
Functional Description
Functional Description
Frame Pulse
2.048Mb/s
8.192Mb/s
10
and A
9
being low)
System Bus
2.048Mb/s
8.192Mb/s
Advance Information

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